Datasheet

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Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0
15/25
WPMDM1500602/ 171050601
MagI³C Power Module
VDRM - Variable Step Down Regulator Module
DESIGN FLOW
V
IN
VIN
FB
PGND
VOUT
Module
R
FBT
R
FBB
C
OUT
AGND
6
7
C
IN
1
EP 4
V
OUT
Based on those considerations, the path of the input capacitor C
IN
is the most critical one to generate high frequency
noise on Vin. Therefore place C
IN
as close as possible to the MagI³C power module V
IN
and PGND exposed pad EP.
This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output
capacitor should consist of a localized top side plane that connects to the PGND exposed pad.
2: Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin of the
device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
Provide the single point ground connection from AGND pin 4 to the GND terminal of the output capacitor. This is the
point of lowest noise.
3: Minimize trace length to the FB pin.
The feedback resistors, R
FBT
and R
FBB
, and the feed forward capacitor C
FF
, should be located close to the FB pin.
Since the FB node is high impedance, maintain the copper area as small as possible. The traces from R
FBT
, R
FBB
,
and C
FF
should be routed away from the body of the MagI³C power module to minimize noise pickup.
4: Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency.
5: Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the
PCB has a plurality of copper layers, these thermal vias can also be used to make connection to inner layer heat-
spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 254μm thermal vias
spaced 1.5mm. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.