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PicoBlaze 8-bit

Embedded Microcontroller

User Guide

for Spartan-3, Virtex-II, and

Virtex-II Pro FPGAs

UG129 (v1.1.2) June 24, 2008

Summary of content (124 pages)

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PicoBlaze 8-bit Embedded Microcontroller User Guide for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs UG129 (v1.1.
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R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
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R Preface Limitations Limited Warranty and Disclaimer These designs are provided to you “as-is”. Xilinx and its licensors make and you receive no warranties or conditions, express, implied, statutory or otherwise, and Xilinx specifically disclaims any implied warranties of merchantability, non-infringement, or fitness for a particular purpose.
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R Preface: Acknowledgments Acknowledgments Xilinx thanks the following individuals for their contribution to the PicoBlaze microcontroller cause: 4 • Henk van Kampen, Mediatronix Developer of the pBlazIDE graphical, integrated development environment. • Prof. Dr.-Ing. Bernhard Lang, University of Applied Sciences, Osrabrueck, Germany Concept of using VHDL simulation variables to display disassembled op-code instructions. • Kris Chaplin, Xilinx Ltd. JTAG-based program loader, update function. www.
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R Guide Contents About This Guide The PicoBlaze™ embedded microcontroller is an efficient, cost-effective embedded processor core for Spartan®-3, Virtex®-II, and Virtex-II Pro FPGAs. This user guide describes the capabilities, features, and benefits of PicoBlaze hardware design and how to effectively use the PicoBlaze instruction set and tools to create software applications.
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R 6 Preface: About This Guide www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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Table of Contents Preface: Limitations Limited Warranty and Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limitation of Liability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Technical Support Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Preface: Acknowledgments ²: About This Guide Guide Contents . . . . . . . . . . . . .
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R Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Negate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R Chapter 8: Performance Input Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Predicting Executing Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Chapter 9: PicoBlaze Development Tools KCPSM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Assembler . . . . . . . . . . . . . . . . . .
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R Appendix A: Related Materials and References Appendix B: Example Program Templates KCPSM3 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 pBlazIDE Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Appendix C: PicoBlaze Instruction Set and Event Reference ADD sX, Operand —Add Operand to Register sX . . . . . . . . . . . . . . . . . . . . . . . .
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R Chapter 1 Introduction The PicoBlaze™ microcontroller is a compact, capable, and cost-effective fully embedded 8-bit RISC microcontroller core optimized for the Spartan®-3, Virtex®-II, and Virtex-II Pro FPGA families. The PicoBlaze microcontroller provides cost-efficient microcontrollerbased control and simple data processing. The PicoBlaze microcontroller is optimized for efficiency and low deployment cost. It occupies just 96 FPGA slices, or only 12.5% of an XC3S50 FPGA and a miniscule 0.
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R Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags • 64-byte internal scratchpad RAM • 256 input and 256 output ports for easy expansion and enhancement • Automatic 31-location CALL/RETURN stack • Predictable performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex-II Pro FPGA • Fast interrupt response; worst-case 5 clock cycles • Optimized for Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGA architectures—just 96 slices and 0.
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R PicoBlaze Microcontroller Functional Blocks Other memory organizations are possible to accommodate more PicoBlaze controllers within a single FPGA or to enable interactive code updates without recompiling the FPGA design. See Chapter 7, “Instruction Storage Configurations,” for more information.
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R Chapter 1: Introduction Program Counter (PC) The Program Counter (PC) points to the next instruction to be executed. By default, the PC automatically increments to the next instruction location when executing an instruction. Only the JUMP, CALL, RETURN, and RETURNI instructions and the Interrupt and Reset Events modify the default behavior. The PC cannot be directly modified by the application code; computed jump instructions are not supported.
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R Why the PicoBlaze Microcontroller? The data registers and scratchpad RAM are not affected by Reset. See “RESET Event” in Appendix C for more information. Why the PicoBlaze Microcontroller? There are literally dozens of 8-bit microcontroller architectures and instruction sets. Modern FPGAs can efficiently implement practically any 8-bit microcontroller, and available FPGA soft cores support popular instruction sets such as the PIC, 8051, AVR, 6502, 8080, and Z80 microcontrollers.
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R Chapter 1: Introduction performance requirements. A completely parallel implementation is faster but consumes more FPGA resources. A microcontroller embedded within the FPGA provides the best of both worlds. The microcontroller implements non-timing crucial complex control functions while timingcritical or data path functions are best implemented using FPGA logic. For example, a microcontroller cannot respond to events much faster than a few microseconds.
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R Chapter 2 PicoBlaze Interface Signals The top-level interface signals to the PicoBlaze™ microcontroller appear in Figure 2-1 and are described in Table 2-1. Figure 7-1 provides additional detail on the internal structure of the PicoBlaze controller.
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R Table 2-1: Chapter 2: PicoBlaze Interface Signals PicoBlaze Interface Signal Descriptions (Continued) Signal Direction Description PORT_ID[7:0] Output Port Address: The I/O port address appears on this port for two CLK cycles during an INPUT or OUTPUT instruction. READ_STROBE Output Read Strobe: When asserted High, this signal indicates that input data on the IN_PORT[7:0] port was captured to the specified data register during an INPUT instruction.
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R Chapter 3 PicoBlaze Instruction Set Table 3-1 summarizes the entire PicoBlaze™ processor instruction set, which appears alphabetically. Instructions are listed using the KCPSM3 syntax. If different, the pBlazIDE syntax appears in parentheses. Each instruction includes an overview description, a functional description, and how the ZERO and CARRY flags are affected. For more details on each instruction, see Appendix C, “PicoBlaze Instruction Set and Event Reference.
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R Table 3-1: Chapter 3: PicoBlaze Instruction Set PicoBlaze Instruction Set (alphabetical listing) Instruction Description Function ZERO CARRY ENABLE INTERRUPT (EINT) Enable interrupt input INTERRUPT_ENABLE Å 1 - - Interrupt Event Asynchronous interrupt input. Preserve flags and PC. Clear INTERRUPT_ENABLE flag. Jump to interrupt vector at address 3FF.
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R Table 3-1: PicoBlaze Instruction Set (alphabetical listing) Instruction RETURNI DISABLE (RETI DISABLE) Description Return from interrupt service routine. Interrupt remains disabled. Function PC Å TOS ZERO CARRY ? ? ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? 0 ? ? ? ? ? ZERO Å Preserved ZERO CARRY Å Preserved CARRY INTERRUPT_ENABLE Å 0 RETURNI ENABLE (RETI ENABLE) Return from interrupt service routine. Re-enable interrupt.
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R Table 3-1: Chapter 3: PicoBlaze Instruction Set PicoBlaze Instruction Set (alphabetical listing) Instruction TEST sX, kk TEST sX, sY Description Function ZERO CARRY Test bits in register sX against literal kk. Update CARRY and ZERO flags. Registers are unaffected. If (sX AND kk) = 0, ZERO Å 1 ? ? ? ? CARRY Å odd parity of (sX AND kk) If (sX AND sY) = 0, ZERO Å 1 Test bits in register sX against register sX. Update CARRY and ZERO flags. Registers are unaffected.
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R Address Spaces Table 3-2: PicoBlaze Address Spaces and Related Instructions Address Space Instruction Size (Depth x Width) Addressing Modes 1Kx18 Direct Instructions that Operate on Address Space • • • • • • JUMP CALL RETURN RETURNI INTERRUPT event RESET event All others increment the PC to the next location Register File 16x8 Direct • • • • • • • • • • • • • • • • • • • • • • • • Scratchpad RAM 64x8 Direct • STORE • FETCH Indirect I/O 256x8 Direct Indirect CALL/RETURN Stack 31x10
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R Chapter 3: PicoBlaze Instruction Set Processing Data All data processing instructions operate on any of the 16 general-purpose registers. Only the data processing instructions modify the ZERO or CARRY flags as appropriate for the instruction.
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R Processing Data Complement/Invert Register The PicoBlaze microcontroller does not have a specific instruction to invert individual bits within register sX. However, the XOR sX,FF instruction performs the equivalent operation, as shown in Figure 3-2. T complement: ; XOR sX, FF If reading this document in Adobe Acrobat, use the Select Text tool to select code snippets, then copy and paste the text into your text editor.
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R Chapter 3: PicoBlaze Instruction Set operation. ORing register sX with a bit mask sets specific bits, as shown in Figure 3-6. A ‘1’ in the bit mask sets the corresponding bit in register sX. A ‘0’ in the bit mask leaves the corresponding bit unchanged. set_bit: ; OR sX, OR s0, 01 ; set bit 0 of register s0 Figure 3-6: 16-Setting a Bit Location Clear Bit The PicoBlaze microcontroller does not have a specific instruction to clear an individual bit or bits within a specific register.
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R Processing Data ADD16: NAMEREG NAMEREG NAMEREG NAMEREG s0, s1, s2, s3, a_lsb a_msb b_lsb b_msb ADD a_lsb, b_lsb ADDCY a_msb, b_msb RETURN Figure 3-8: ; ; ; ; rename rename rename rename register register register register s0 s1 s2 s3 as as as as “a_lsb” “a_msb” “b_lsb” “b_lsb” ; add LSBs, keep result in a_lsb ; add MSBs, keep result in a_msb 16-Bit Addition Using ADD and ADDCY Instructions See also: • “ADD sX, Operand —Add Operand to Register sX,” page 91 • “ADDCY sX, Operand —Add Operan
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R Chapter 3: PicoBlaze Instruction Set ADD sX,01 ; increment register sX SUB sX,01 ; decrement register sX Figure 3-10: Incrementing and Decrementing a Register If incrementing or decrementing a multi-register value—i.e., a 16-bit value—perform the operation using multiple instructions. Incrementing or decrementing a multi-byte value requires using the add or subtract instructions with carry, as shown in Figure 3-11.
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R Processing Data ; Multiplier Routine (8-bit x 8-bit = 16-bit product) ; ================================================== ; Shift and add algorithm ; mult_8x8: ; preserved NAMEREG s0, multiplicand NAMEREG s1, multiplier ; preserved NAMEREG s2, bit_mask ; modified NAMEREG s3, result_msb ; most-significant byte (MSB) of result, ; modified NAMEREG s4, result_lsb ; least-significant byte (LSB) of result, ; modified ; LOAD bit_mask, 01 ; start with least-significant bit (lsb) LOAD result_msb, 00 ; clear pro
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R Chapter 3: PicoBlaze Instruction Set 18x18 Multiplier A[17:8] PicoBlaze Microcontroller 1 IN_PORT[7:0] OUT_PORT[7:0] PORT_ID[7:0] 0 SEL A[7:0] P[15:8] EN [0] P[7:0] READ_STROBE B[17:8] WRITE_STROBE B[7:0] EN UG129_c3_02_052004 Figure 3-15: 8-bit by 8-bit Hardware Multiplier Using the FPGA’s 18x18 Multipliers ; Multiplier Routine (8-bit x 8-bit = 16-bit product) ; =================================================== ; Connects to embedded 18x18 Hardware Multiplier via ports ; mult_8x8io: NAM
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R Processing Data ; Divide Routine (8-bit / 8-bit = 8-bit result, remainder) ; ================================================== ; Shift and subtract algorithm ; div_8by8: NAMEREG s0, dividend ; preserved NAMEREG s1, divisor ; preserved NAMEREG s2, quotient ; preserved NAMEREG s3, remainder ; modified NAMEREG s4, bit_mask ; used to test bits in dividend, ; one-hot encoded, modified ; LOAD remainder, 00 ; clear remainder LOAD bit_mask, 80 ; start with most-significant bit (msb) div_loop: TEST dividend, bi
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R Chapter 3: PicoBlaze Instruction Set A similar NOP technique is to simply jump to the next instruction, which is equivalent to the default program flow. The JUMP instruction consumes an instruction cycle (two clock cycles) without affecting register contents.
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R Processing Data Register sY Literal kk 7 6 Register sX 5 7 4 6 3 5 2 4 1 3 0 2 1 0 Bitwise AND If all bit results are zero, set ZERO flag. ZERO Figure 3-22: UG129_c3_03_051404 The TEST Instruction Affects the ZERO Flag Each bit of register sX is logically ANDed with either the contents of register sY or a literal constant, kk. The operation sets the ZERO flag if the result of all bitwise AND operations is zero.
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R Chapter 3: PicoBlaze Instruction Set The example in Figure 3-25 demonstrates how to generate parity for all eight bits in a register. generate_parity: TEST sX, FF ; include all bits in parity generation Figure 3-25: Generate Parity for a Register Using the TEST Instruction See also “TEST sX, Operand — Test Bit Location in Register sX, Generate Odd Parity,” page 116.
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R Processing Data Table 3-4: PicoBlaze Shift Instructions Shift Left Shift Left with ‘0’ fill. SL0 7 6 5 4 3 Register sX 2 1 ‘0’ 0 Shift Left with ‘1’ fill. SL1 ‘0’ 7 6 7 6 5 4 3 2 1 ‘1’ 0 ‘1’ 7 6 6 5 4 3 2 1 0 7 6 5 4 3 5 SRA 6 1 0 4 3 2 CARRY 1 0 2 5 4 3 2 CARRY 1 0 Shift Right through All bits, including CARRY. Register sX 7 2 Register sX Shift Left through All bits, including CARRY. CARRY 3 Shift Right, sign eXtend.
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R Chapter 3: PicoBlaze Instruction Set Moving Data Data movement between various resources is an essential microcontroller function. Figure 3-26 shows the various PicoBlaze instructions to move data.
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R Program Flow Control The JUMP, CALL, and RETURN instructions are all conditionally executed, depending if a condition is specified and specifically whether the CARRY or ZERO flags are set or cleared. Table 3-6 summarizes the possible conditions. The condition is specified as an instruction operand. The instruction is unconditionally executed if no condition is specified. Table 3-6: Instruction Conditional Execution Condition C NC Z NZ Description Always true.
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R Chapter 3: PicoBlaze Instruction Set ADDRESS 000 main: JUMP C, skip_over If CARRY is set, load the PC with the address of the label skip_over. A CALL my_subroutine ADD s0, s1 skip_over: 3 1 Call my_subroutine. Save the current PC to top of CALL/ RETURN stack. Load the PC with the address of my_subroutine. JUMP main my_subroutine: 2 Return from my_subroutine. Load the PC with the top of the CALL/ RETURN stack plus 1. Execute the instruction immediately following the associated CALL instruction.
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R Program Flow Control RETURN instructions themselves. If the CALL instruction is not executed, then the flags are unaffected. See also: • “CALL [Condition,] Address — Call Subroutine at Specified Address, Possibly with Conditions,” page 94“ • “RETURN [Condition] — Return from Subroutine Call, Possibly with Conditions,” page 106 PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.2) June 24, 2008 www.xilinx.
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R 40 Chapter 3: PicoBlaze Instruction Set www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Chapter 4 Interrupts The PicoBlaze™ processor provides a single interrupt input signal. If the application requires multiple interrupt signals, combine the signals using simple FPGA logic to form a single INTERRUPT input signal. After reset, the INTERRUPT input is disabled and must be enabled via the ENABLE INTERRUPT instruction. To disable interrupts at any point in the program, issue a DISABLE INTERRUPT instruction.
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R Chapter 4: Interrupts A special RETURNI command ensures that the end of an interrupt service routine restores the status of the flags and controls the enable of future interrupts. When the RETURNI instruction is executed, the PC values saved onto the CALL/RETURN stack is automatically reloaded to the PC register. Likewise, the ZERO and CARRY flags are restored and program flow returns to the instruction following the instruction where the interrupt occurred.
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R Example Interrupt Flow 3. The PicoBlaze microcontroller recognizes the interrupt and preempts the ADD s0,s1 instruction. The current PC, which points to the ADD s0 s1 instruction, is pushed onto the CALL/RETURN stack. Likewise, the ZERO and CARRY flags are preserved. Furthermore, the INTERRUPT_ENABLE flag is cleared disabling any further interrupts.
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R Chapter 4: Interrupts Figure 4-3 shows the same interrupt procedure but as a timing diagram. With the interrupt enabled, the INTERRUPT input is recognized at Step (2), the same clock cycle where the ADDRESS bus changes value. The address for the instruction ADD s0,s1 appears on the ADDRESS bus and is pushed onto the CALL/RETURN stack. Simultaneously, the interrupt is disabled and the ZERO and CARRY flags are preserved. The ADD s0, s1 instruction is preempted and does not yet execute.
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R Chapter 5 Scratchpad RAM The PicoBlaze™ microcontroller contains a 64-byte scratchpad RAM. Two instructions, STORE and FETCH, move data between any data register and the scratchpad RAM. Both direct and indirect addressing are supported. The scratchpad RAM is only supported on PicoBlaze microcontrollers for Spartan®-3, Virtex®-II, and Virtex-II Pro FPGAs. The scratchpad RAM is unaffected by a RESET Event.
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R Chapter 5: Scratchpad RAM NAMEREG s0, ram_data NAMEREG s1, ram_address CONSTANT ram_locations, 40 CONSTANT initial_value, 00 ; there are 64 locations ; initialize to zero LOAD ram_data, initial_value ; load initial value LOAD ram_address, ram_locations ; fill from top to bottom ram_fill: SUB ram_address, 01 STORE ram_data, (ram_address) JUMP NZ, ram_fill ; ; ; ; decrement address initialize location if not address 0, goto ram_fill Figure 5-2: Indirect Addressing Initializes All of RAM with a Simple
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R Stack Operations Stack Operations Although the PicoBlaze microcontroller has a CALL/RETURN stack, it does not have a dedicated data stack. In some controller architectures, register values are preserved during subroutine calls or interrupts by pushing them or popping them onto a data stack. The equivalent operation is possible in the PicoBlaze microcontroller by reserving some locations in scratchpad RAM. In the example shown in Figure 5-4, the my_subroutine function uses register s0.
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R 48 Chapter 5: Scratchpad RAM www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Chapter 6 Input and Output Ports The PicoBlaze™ microcontroller supports up to 256 input ports and 256 output ports that can also be combined to create input/output ports. The interface signals from Figure 2-1 involved in INPUT and OUTPUT operations are described below. • The PORT_ID[7:0] output port presents the port identifier number or port address for both INPUT and OUTPUT operations. • The IN_PORT[7:0] input port captures input data during INPUT operations.
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R Chapter 6: Input and Output Ports Table 6-1: Decoding PORT_ID Depending on Number of Ports Number of Ports INPUT OUTPUT 0 to 1 No multiplexing required No decoding required 2 to 8 Single input multiplexer “One hot” encode PORT_ID Binary encode PORT_ID 9 to 256 Cascaded multiplexer tree Binary encode PORT_ID Binary encode PORT_ID Hybrid “one hot”/binary encoded INPUT Operations An INPUT operation transfers the data supplied on the IN_PORT input port to any one of the 16 data registers, de
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R INPUT Operations The PicoBlaze microcontroller captures the value on IN_PORT[7:0] into register s0 on this clock edge. 1 0 2 3 4 CLK INSTRUCTION[17:0] INPUT s0,(s7) Contents of register s7 PORT_ID[7:0] IN_PORT[7:0] READ_STROBE Captured Value from IN_PORT[7:0] Register s0 UG129_c6_02_060404 Figure 6-2: Port Timing for INPUT Instruction In this example, the PicoBlaze microcontroller is reading data from the port address defined by the contents of register s7.
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R Chapter 6: Input and Output Ports IN_D 11 IN_C 10 Registering the multiplexer output is allowed because PORT_ID is asserted for two clock cycles. Registering improves performance.
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R OUTPUT Operations PicoBlaze Microcontroller IN_PORT[7:0] OUT_PORT[7:0] PORT_ID[7:0] 01 If performance is adequate, remove the flip-flip and combine the READ_STROBE and PORT_ID decode logic. READ_STROBE WRITE_STROBE FIFO READ DATA_OUT 00 S0 S1 READ_STROBE PORT_ID[1] PORT_ID[0] UG129_c6_04_060404 Figure 6-4: READ_STROBE Indicates a Successful INPUT Operation OUTPUT Operations As shown in Figure 6-5, an OUTPUT operation presents the contents of any of the 16 registers to the OUT_PORT output port.
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R Chapter 6: Input and Output Ports Use WRITE_STROBE as the clock enable to capture output values in FPGA logic.
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R OUTPUT Operations PORT_C [2] D Q EN PORT_B [1] D Q EN PORT_A PicoBlaze Microcontroller IN_PORT[7:0] [0] D Q EN OUT_PORT[7:0] PORT_ID[7:0] READ_STROBE WRITE_STROBE UG129_c6_07_052004 Figure 6-7: Simple Address Decoding for Designs with Few Output Destinations As shown in Figure 6-8, use CONSTANT directives in the program make the code readable and help ensure that the correct ports are decoded.
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R Chapter 6: Input and Output Ports Pipelining for Maximum Performance In most applications, the PicoBlaze microcontroller has more than sufficient performance to meet application requirements. However, PicoBlaze designs attached to multiple memory blocks or that have many simple ports may end up using most, if not all, of the 256 available port addresses. Decoding and routing all 256 locations complicates the overall design, especially for designs requiring maximum performance.
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R Pipelining for Maximum Performance The pipelining registers on the OUT_PORT and PORT_ID signals, shaded in Figure 6-9, are optional. Both OUT_PORT and PORT_ID are valid for two clock cycles. However, pipelining them decreases the initial fanout and reduces the routing distance, both of which improve performance. During OUTPUT operations, the PicoBlaze microcontroller has no data dependencies and consequently no dependencies on the FPGA interface logic.
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R Chapter 6: Input and Output Ports PicoBlaze Microcontroller 1 0 S2 UG129_c6_10_060404 Figure 6-11: Effective Pipelining Improves Read Performance Repartitioning the Design for Maximum Performance Another approach to maximizing performance is to re-evaluate the system requirements. If the number of I/O ports is the bottleneck in the system, ask if all the ports are actually required as part of a single application or whether a single PicoBlaze microcontroller is performing multiple tasks.
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R Chapter 7 Instruction Storage Configurations The PicoBlaze™ microcontroller executes code from memory resources embedded within the FPGA. Figure 7-1 shows that the PicoBlaze microcontroller actually consists of two subfunctions. The KCPSM3 module contains the PicoBlaze ALU, register file, scratchpad RAM, etc. Some form of internal memory, typically a block RAM, provides the PicoBlaze instruction store.
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R Chapter 7: Instruction Storage Configurations Block RAM KCPSM3 (1Kx18) 18 DOP[1:0] DO[15:0] INSTRUCTION[17:0] ADDR[9:0] ADDRESS[9:0] 10 UG129_c7_02_051504 Figure 7-2: Standard Configuration using a Single 1Kx18 Block RAM Standard Configuration with UART or JTAG Programming Interface The second read/write port on the block RAM provides a convenient means to update the PicoBlaze instruction store without recompiling the entire FPGA design.
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R Two PicoBlaze Microcontrollers with Separate 512x18 Code Images in a Block RAM Two PicoBlaze Microcontrollers with Separate 512x18 Code Images in a Block RAM Two PicoBlaze microcontrollers can also share a single dual-port RAM but each with a separate 512-instruction area, as shown in Figure 7-5. The most-significant address bit of one block RAM port is tied Low while the other same bit on the other port is tied High. This limits each port to half of the 1Kx18 memory, or 512x18.
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R Chapter 7: Instruction Storage Configurations To maintain compatibility with block RAM, the distributed ROM must have a registered output using CLB flip-flops. Table 7-1: Slices Required when Using CLBs for ROM Instructions ROM Slices < 16 9 < 32 18 < 64 36 < 128 72 < 256 144 < 512 297 < 1,024 594 The CORE Generator software can create all of the above distributed ROM functions using the coefficients file generated by the PicoBlaze assembler. 62 www.xilinx.
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R Chapter 8 Performance Input Clock Frequency Table 8-1 shows the maximum available performance for the PicoBlaze™ microcontroller using various FPGA families and speed grades. The Virtex®-II and Virtex-II Pro FPGA families are optimized for maximum performance. The Spartan®-3 FPGA family is optimized for lowest cost.
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R 64 Chapter 8: Performance www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Chapter 9 PicoBlaze Development Tools There are three primary development environments for creating PicoBlaze™ processor application code, as summarized in Table 9-1. Xilinx offers two PicoBlaze environments. The PicoBlaze reference design includes the KCPSM3 command-line assembler that executes in a Windows DOS box or command window. The Xilinx System Generator for DSP development environment includes both a PicoBlaze assembler and a simulation model for the Math Works MATLAB/Simulink environment.
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R Chapter 9: PicoBlaze Development Tools Open a DOS box and navigate to the working directory. To assemble the PicoBlaze program, type: kcpsm3 [.psm] Assembly Errors The assembler halts as soon as an error is detected. A short message indicates the reason for any error. The assembler also displays the line that it was analyzing when it detected the problem. Fix each reported problem in turn and re-execute the assembler.
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R Mediatronix pBlazIDE The assembler also produces a log file plus files that show the assignments for various labels and constants found in the source code. The log file shows the instruction address, the opcode for each instruction, and the source code instruction and comments for the associated instruction address. The assigned values for register names, labels, and constants appear immediately following the associated symbolic name.
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R Chapter 9: PicoBlaze Development Tools Importing KCPSM3 Code into pBlazIDE The pBlazIDE syntax and instruction mnemonics are different than the Xilinx KCPSM3 syntax. The pBlazIDE software provides an import function to convert KCPSM3 code to the pBlazIDE syntax. From the pBlazIDE menu, choose File Æ Import, then select the KCPSM3-format *.psm file, as shown in Figure 9-3. The pBlazIDE software automatically translates and formats the source code, as shown in Figure 9-4.
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R Differences Between the KCPSM3 Assembler and pBlazIDE Differences Between the KCPSM3 Assembler and pBlazIDE Table 9-2 details the differences between the KCPSM3 and pBlazIDE instruction mnemonics.
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R 70 Chapter 9: PicoBlaze Development Tools www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Chapter 10 Using the PicoBlaze Microcontroller in an FPGA Design The PicoBlaze™ microcontroller is primarily designed for use in a VHDL design flow. However, both Verilog and black box instantiation are also supported, as described below. Similarly, Xilinx XST/ISE® 6.2i and later versions support mixed language support where both VHDL and Verilog can be mixed in a single project. There is also support for the Xilinx System Generator design environment.
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R Chapter 10: Using the PicoBlaze Microcontroller in an FPGA Design processor: kcpsm3 port map( address instruction port_id write_strobe out_port read_strobe in_port interrupt interrupt_ack reset clk => => => => => => => => => => => address_signal, instruction_signal, port_id_signal, write_strobe_signal, out_port_signal, read_strobe_signal, in_port_signal, interrupt_signal, interrupt_ack_signal, reset_signal, clk_signal ); Figure 10-2: VHDL Component Instantiation of the KCPSM3 Connecting the Progra
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Black Box Instantiation of KCPSM3 using KCPSM3.ngc R Black Box Instantiation of KCPSM3 using KCPSM3.ngc The Xilinx NGC file included with the reference design was generated by synthesizing the KCPSM3.vhd file using the Xilinx Synthesis Tool (XST), without inserting I/O buffers. When used as a “black box” in a Spartan-3, Virtex-II or Virtex-II Pro FPGA design, the PicoBlaze microcontroller is merged with the remainder of the FPGA design during the translate phase (ngdbuild).
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R 74 Chapter 10: Using the PicoBlaze Microcontroller in an FPGA Design www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Chapter 11 Assembler Directives Both the KCPSM3 and pBlazIDE assemblers include directives that provide advanced control. Locating Code at a Specific Address In some cases, application code must be assigned to a specific instruction address. Examples include the code located at the reset vector, 0, and the interrupt vector, 3FF. As an example, Table 11-1 shows the PicoBlaze™ processor assembler directive to locate code at the interrupt vector for both the KCPSM3 and pBlazIDE formats.
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R Chapter 11: Assembler Directives Defining Constants Similar to renaming registers, assign names to constant values. By defining names for constants, it is easier to understand and document the PicoBlaze code rather than using the constant values in the code. Similarly, assigning names to registers and constants simplifies code maintenance. Updating the value assigned to a constant is easier if the constant is declared just once rather than searching for each occurrence in the application code.
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R Defining I/O Ports (pBlazIDE) Input Ports The DSIN directive defines the name and the port address (or port identification number) for a read-only input port. The DSIN directive models an input port that only connects to the PicoBlaze microcontroller’s IN_PORT port. An optional field specifies a text file containing input values used during instruction set simulation. Figure 11-2 provides an example.
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R Chapter 11: Assembler Directives specifies a text file that records the result of any output operations to this during instruction set simulation. Figure 11-5 provides an example. ; pBlazIDE syntax to define a write-only output port ; output_port_name DSOUT [, “”] ; LEDs DSOUT $01, “output_values.txt” writeport DSOUT $1E Figure 11-5: Example of pBlazIDE DSOUT Directive The values recorded in the optional output file are always written as hexadecimal values.
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R Custom Instruction Op-Codes During instruction set simulation, pBlazIDE displays the readable output port as shown in Figure 11-8. The port value can be modified from the graphical interface. User-defined input/ output port name. Port address (Port ID #) Current port value. Double-click to edit. input_output_port_name $02 $F0 7 6 5 4 3 2 1 0 Click LED to set or clear bit for input.
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R 80 Chapter 11: Assembler Directives www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Chapter 12 Simulating PicoBlaze Code Various tools support PicoBlaze code simulation, each with distinct strengths and weaknesses as described in Table 12-1. For example, the pBlazIDE Instruction Set Simulator (ISS) is best for simulating PicoBlaze operation during code development. As shown in Figure 12-1, the pBlazIDE ISS provides a seamless development environment where assembly code can be quickly tested with full observability. Registers, flags, and memory values appear on the graphical display.
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R Table 12-1: Chapter 12: Simulating PicoBlaze Code PicoBlaze Code Simulation Options Verification Tool Strengths Weaknesses Xilinx System Generator • Full PicoBlaze system-level simulation • Primarily only useful is already using with the System Generator environment Xilinx System Generator • Cycle-accurate Instruction Set Simulation (ISS) • Single-step • Breakpoints • Register and memory viewer In-system on FPGA • Fast, real-time performance • Ideal for complex interactions • Integrated with per
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R Instruction Set Simulation with pBlazIDE Simulation control buttons pBlaze IDE File Status flags Edit View Settings Status $00 $01 $02 Zero Carry Enable Interrupt control for simulation Help Register aliasing s3 s4 mailbox input_value LED_output EQU Input, EQU $80 threshold_value EQU $80 Edge ORG 0 start : Timer Instruction $000 $3C001 address 50 Data registers Instruction code Registers poll_loop 00 8 1 00 00 9 2 00 00 A 3 27 00 B $004 $2C401 4 F0 00 C $005 $34001
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R Table 12-2: Chapter 12: Simulating PicoBlaze Code pBlazIDE Simulator Control Buttons (Continued) Button Function Reset Reset the simulator. Reset the Program Counter (PC) and Stack Pointer (SP). Register and RAM values are not reset. Run Single Step Step Over Run to Cursor Pause Toggle Breakpoint Remove All Breakpoints Run the program. The program continues running until an active breakpoint is encountered or if the Reset or Pause button is pressed. Execute a single instruction.
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R Turbocharging Simulation using FPGAs! Turbocharging Simulation using FPGAs! Hardware simulators track results with picosecond or nanosecond resolution. In contrast, the PicoBlaze microcontroller is often employed in applications that are less time critical or deliberately slow. For example, a real-time clock is impractical to simulate using a hardware or software simulator. Even UART-based communication is desperately slow relative to a 50 MHz system clock.
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R 86 Chapter 12: Simulating PicoBlaze Code www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Appendix A Related Materials and References This appendix provides links to additional information relevant to a PicoBlaze™ processor design. 1. PicoBlaze 8-bit Embedded Microcontroller Download PicoBlaze reference designs and additional files. http://www.xilinx.com/ipcenter/processor_central/picoblaze 2. Mediatronix pBlazIDE Integrated Development Environment for PicoBlaze http://www.mediatronix.com/pBlazeIDE.htm 3.
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R 88 Chapter : Related Materials and References www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Appendix B Example Program Templates The following code templates provide the basic recommended structure for PicoBlaze™ processor application programs. Both KCPSM3 and pBlazIDE templates are provided. T If reading this document in Adobe Acrobat, use the Select Text tool to select code snippets, then copy and paste the text into your text editor. KCPSM3 Syntax Figure B-1 provides a code template for creating PicoBlaze applications using the KCPSM3 assembler.
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R Appendix : Example Program Templates pBlazIDE Syntax Figure B-2 provides a code template for creating PicoBlaze applications using the pBlazIDE assembler. EQU sX EQU $00 ; Rename register sX with ; Define constant , assign value ; name ROM output file generated by pBlazIDE assembler VHDL “template.vhd”, “target.
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R Appendix C PicoBlaze Instruction Set and Event Reference This appendix provides a detailed operational description of each PicoBlaze™ processor instruction and the Interrupt and Reset events, including pseudocode for each instruction. The pseudocode assumes that all variable to the right of an assignment symbol (Å) have the original value before the instruction is executed.
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R Appendix : PicoBlaze Instruction Set and Event Reference Pseudocode sX Å (sX + Operand) mod 256; always an 8-bit result if ( (sX + Operand) > 255 ) then CARRY Å 1 else CARRY Å 0 endif if ( ((sX + Operand) = 0) or ((sX + Operand) = 256) ) then ZERO Å 1 else ZERO Å 0 endif PC Å PC + 1 Registers/Flags Altered Registers: sX, PC Flags: CARRY, ZERO ADDCY sX, Operand —Add Operand to Register sX with Carry The ADDCY instruction performs an addition of two 8-bit operands and adds an additional ‘1’ if the CARRY
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R AND sX, Operand — Logical Bitwise AND Register sX with Operand Pseudocode if (CARRY = 1) then sX Å (sX + Operand + 1) mod 256; always an 8-bit result else sX Å (sX + Operand) mod 256 ; always an 8-bit result end if if ( (sX + Operand + CARRY) > 255 ) then CARRY Å 1 else CARRY Å 0 endif if ( ((sX + Operand + CARRY) = 0) or ((sX + Operand + CARRY) = 256) ) then ZERO Å 1 else ZERO Å 0 endif PC Å PC + 1 Registers/Flags Altered Registers: sX, PC Flags: CARRY, ZERO Notes pBlazIDE Equivalent: ADDC AND sX, Op
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R Appendix : PicoBlaze Instruction Set and Event Reference Examples AND sX, sY AND sX, kk ; ; ; ; Logically AND the the corresponding Logically AND the the corresponding individual bits of register sX with bits in register sY individual bits of register sX with bits in the immediate constant kk Pseudocode ; logically AND the corresponding bits in sX and the Operand for (i=0; i<= 7; i=i+1) { sX(i) Å sX(i) AND Operand(i) } CARRY Å 0 if (sX = 0) then ZERO Å 1 else ZERO Å 0 end if PC Å PC + 1 Registers/F
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CALL [Condition,] Address — Call Subroutine at Specified Address, Possibly with Conditions R Condition Depending on the specified Condition, the program calls the subroutine beginning at the specified Address. If the specified Condition is not met, the program continues to the next instruction. Table C-1: CALL Instruction Conditions Condition C NC Z NZ Description Always true. Call subroutine unconditionally. CARRY = 1. Call subroutine if CARRY flag is set. CARRY = 0.
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R Appendix : PicoBlaze Instruction Set and Event Reference COMPARE sX, Operand — Compare Operand with Register sX The COMPARE instruction performs an 8-bit comparison of two operands, as shown in Figure C-4. The first operand, sX, is any register and this register is NOT affected by the COMPARE operation. The second operand is also any register or an 8-bit immediate constant value. Only the flags are affected by this operation.
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DISABLE INTERRUPT — Disable External Interrupt Input R DISABLE INTERRUPT — Disable External Interrupt Input The DISABLE INTERRUPT instruction clears the interrupt enable (IE) flag. Consequently, the PicoBlaze microcontroller ignores the INTERRUPT input. Use this instruction to temporarily disable interrupts during timing-critical code segments. Use the ENABLE INTERRUPT instruction to re-enable interrupts.
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R Appendix : PicoBlaze Instruction Set and Event Reference FETCH sX, Operand — Read Scratchpad RAM Location to Register sX The FETCH instruction reads scratchpad RAM location specified by Operand into register sX, as shown in Figure C-5. There are 64 scratchpad RAM locations. The two mostsignificant bits of Operand, bits 7 and 6, are discarded and the RAM address is truncated to the least-significant six bits of Operand, bits 5 to bit 0.
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R INPUT sX, Operand — Set PORT_ID to Operand, Read value on IN_PORT into Register sX INPUT sX, Operand — Set PORT_ID to Operand, Read value on IN_PORT into Register sX The INPUT instruction sets the PORT_ID output port to either the value specified by register sY or by the immediate constant kk. The instruction then reads the value on the IN_PORT input port into register sX. Flags are not affected by this operation. Interface logic decodes the PORT_ID address to provide the correct value on IN_PORT.
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R Appendix : PicoBlaze Instruction Set and Event Reference INTERRUPT Event, When Enabled The interrupt event is not an instruction but the response of the PicoBlaze microcontroller to an external interrupt input. If the INTERRUPT_ENABLE flag is set, then a recognized logic level on the INTERRUPT input generates an Interrupt Event. The action essentially generates a subroutine CALL to the most-significant instruction address, location 1023 ($3FF). The currently executing instruction is allowed to complete.
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R JUMP [Condition,] Address — Jump to Specified Address, Possibly with Conditions JUMP [Condition,] Address — Jump to Specified Address, Possibly with Conditions The JUMP instruction modifies the normal program execution sequence by jumping to a specified program address. Each JUMP instruction must specify the 10-bit address as a three-digit hexadecimal value or a label that the assembler resolves to a three-digit hexadecimal value. The JUMP instruction has both conditional and unconditional variants.
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R Appendix : PicoBlaze Instruction Set and Event Reference LOAD sX, Operand — Load Register sX with Operand The LOAD instruction loads the contents of any register. The new value is either the contents of any other register or an immediate constant. The LOAD instruction has no effect on the status flags. Because the LOAD instruction does not affect the flags, use it to reorder and assign register contents at any stage of the program execution.
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R OR sX, Operand — Logical Bitwise OR Register sX with Operand OR sX, Operand — Logical Bitwise OR Register sX with Operand The OR instruction performs a bitwise logical OR operation between two operands, as shown in Figure C-6. The first operand is any register, which also receives the result of the operation. A second operand is also any register or an 8-bit immediate constant. The ZERO flag is set if the resulting value is zero. The CARRY flag is always cleared by an OR instruction.
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R Appendix : PicoBlaze Instruction Set and Event Reference OUTPUT sX, Operand — Write Register sX Value to OUT_PORT, Set PORT_ID to Operand The OUTPUT instruction sets the PORT_ID port address to the value specified by either the register sY or the immediate constant kk. The instruction writes the contents of register sX to the OUT_PORT output port. FPGA logic captures the output value by decoding the PORT_ID value and WRITE_STROBE output, as shown in Figure C-7.
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R RESET Event RESET Event The reset event is not an instruction but the response of the PicoBlaze microcontroller when the RESET input is High. A RESET Event restarts the PicoBlaze microcontroller and clears various hardware elements, as shown in Table C-3. A RESET Event is automatically generated immediately following FPGA configuration, initiated by the FPGA’s internal Global Set/Reset (GSR) signal.
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R Appendix : PicoBlaze Instruction Set and Event Reference RETURN [Condition] — Return from Subroutine Call, Possibly with Conditions The RETURN instruction is the complement to the CALL instruction. The RETURN instruction is also conditional. The new PC value is formed internally by incrementing the last value on the program address stack, ensuring that the program executes the instruction following the CALL instruction that called the subroutine.
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R RETURNI [ENABLE/DISABLE] — Return from Interrupt Service Routine and Enable or Disable PBlazIDE Equivalent: RET, RET C, RET NC, RET Z, RET NZ RETURNI [ENABLE/DISABLE] — Return from Interrupt Service Routine and Enable or Disable Interrupts The RETURNI instruction is a special variation of the RETURN instruction. It concludes an interrupt service routine. The RETURNI instruction is unconditional and pops the return address from the top of the CALL/RETURN stack into the PC.
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R Appendix : PicoBlaze Instruction Set and Event Reference RL sX — Rotate Left Register sX The rotate left instruction operates on any single data register. Each bit in the specified register is shifted left by one bit position, as shown in Table C-5. The most-significant bit, bit 7, shifts both into the CARRY bit and into the least-significant bit, bit 0. Table C-5: Rotate Left (RL) Operation Rotate Left RL sX Register sX CARRY 7 6 5 4 3 2 1 0 Example RL sX; Rotate left.
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R SL[ 0 | 1 | X | A ] sX — Shift Left Register sX Example RR sX; Rotate right. Bit sX[0] copied into CARRY Pseudocode CARRY Å sX[0] sX Å {sX[0], sX[7:1]} if ( sX = 0 ) then ZERO Å 1 else ZERO Å 0 endif PC Å PC + 1 Registers/Flags Altered Registers: sX, PC Flags: CARRY, ZERO SL[ 0 | 1 | X | A ] sX — Shift Left Register sX There are four variants of the shift left instruction, as shown in Table C-7, that operate on any single data register.
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R Appendix : PicoBlaze Instruction Set and Event Reference Examples SL0 SL1 SLX SLA sX; sX; sX; sX; Shift Shift Shift Shift left. left. left. left. 0 shifts into LSB, MSB shifts into CARRY. 1 shifts into LSB, MSB shifts into CARRY. LSB shifts into LSB, MSB shifts into CARRY. CARRY shifts into LSB, MSB shifts into CARRY.
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R SR[ 0 | 1 | X | A ] sX — Shift Right Register sX Table C-8: Shift Right Operations Shift Right Shift Right with ‘0’ fill. SR0 sX Register sX ‘0’ 7 6 5 4 3 2 CARRY 1 0 Shift Right with ‘1’ fill. SR1 sX Register sX ‘1’ 7 6 5 4 3 2 CARRY 1 0 Shift Right, sign eXtend. SRX sX Register sX 7 6 5 4 3 2 CARRY 1 0 Shift Right through All bits, including CARRY.
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R Appendix : PicoBlaze Instruction Set and Event Reference Registers/Flags Altered Registers: sX, PC Flags: CARRY, ZERO STORE sX, Operand — Write Register sX Value to Scratchpad RAM Location The STORE instruction writes register sX to the scratchpad RAM location specified by Operand, as shown in Figure C-8. There are 64 scratchpad RAM locations.
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R SUB sX, Operand —Subtract Operand from Register sX KCPSM3 Instruction PBlazIDE Instruction STORE sX, (sY) STORE sX, sY The STORE instruction is only supported on PicoBlaze microcontrollers for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs. SUB sX, Operand —Subtract Operand from Register sX The SUB instruction performs an 8-bit subtraction of two operands, as shown in Figure C-9. The first operand is any register, which also receives the result of the operation.
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R Appendix : PicoBlaze Instruction Set and Event Reference Pseudocode sX Å (sX – Operand) mod 256; always an 8-bit result if ( (sX – Operand) < 0 ) then CARRY Å 1 else CARRY Å 0 endif if ( (sX - Operand) = 0 ) then ZERO Å 1 else ZERO Å 0 endif PC Å PC + 1 Registers/Flags Altered Registers: sX, PC Flags: CARRY, ZERO SUBCY sX, Operand —Subtract Operand from Register sX with Borrow The SUBCY instruction performs an 8-bit subtraction of two operands and subtracts an additional ‘1’ if the CARRY (borrow) flag
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R SUBCY sX, Operand —Subtract Operand from Register sX with Borrow Description Operand and CARRY flag are subtracted from register sX. The ZERO and CARRY flags are set appropriately.
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R Appendix : PicoBlaze Instruction Set and Event Reference TEST sX, Operand — Test Bit Location in Register sX, Generate Odd Parity The TEST instruction performs two related but separate operations. The ZERO flag indicates the result of a bitwise logical AND operation between register sX and the specified Operand. The ZERO flag is set if the resulting bitwise AND is zero, as shown in Figure C-11.
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R TEST sX, Operand — Test Bit Location in Register sX, Generate Odd Parity Pseudocode ; logically AND the corresponding bits in sX and the Operand for (i=0; i<= 7; i=i+1) { AND_TEST(i) Å sX(i) AND Operand(i) } if (AND_TEST = 0) then ZERO Å 1 else ZERO Å 0 end if ; logically XOR the corresponding bits in sX and the Operand XOR_TEST = 0 for (i=0; i<= 7; i=i+1) { XOR_TEST Å AND_TEST(i) XOR XOR_TEST } if (XOR_TEST = 1) then; generate odd parity CARRY Å 1 ; odd number of one’s, CARRY=1 for odd parity else CARR
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R Appendix : PicoBlaze Instruction Set and Event Reference XOR sX, Operand — Logical Bitwise XOR Register sX with Operand The XOR instruction performs a bitwise logical XOR operation between two operands, as shown in Figure C-13. The first operand is any register, which also receives the result of the operation. A second operand is also any register or an 8-bit immediate constant. The ZERO flag is set if the resulting value is zero. The CARRY flag is always cleared by an XOR instruction.
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R Appendix D Instruction Codes Table D-1 provides the 18-bit instruction code for every PicoBlaze™ processor instruction.
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R Appendix : Instruction Codes Table D-1: PicoBlaze Instruction Codes (Continued) Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JUMP Z 1 1 0 1 0 1 0 0 a a a a a a a a a a LOAD sX,kk 0 0 0 0 0 0 x x x x k k k k k k k k LOAD sX,sY 0 0 0 0 0 1 x x x x y y y y 0 0 0 0 OR sX,kk 0 0 1 1 0 0 x x x x k k k k k k k k OR sX,sY 0 0 1 1 0 1 x x x x y y y y 0 0 0 0 OUTPUT sX,(sY) 1 0 1 1 0 1 x x
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R Table D-1: PicoBlaze Instruction Codes (Continued) Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XOR sX,kk 0 0 1 1 1 0 x x x x k k k k k k k k XOR sX,sY 0 0 1 1 1 1 x x x x y y y y 0 0 0 0 a Absolute instruction address x Register sX y Register sY k Immediate constant p Port address s Scratchpad RAM address PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.2) June 24, 2008 www.xilinx.
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R 122 Appendix : Instruction Codes www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.
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R Appendix E Register and Scratchpad RAM Planning Worksheets This appendix provides worksheets to plan register assignment and allocation for a PicoBlaze™ processor application. A similar worksheet is also provided to plan scratchpad RAM assignment and allocation. Registers Reg. Description s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 sA sB sC sD sE sF PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.2) June 24, 2008 www.xilinx.
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R Appendix : Register and Scratchpad RAM Planning Worksheets Scratchpad RAM Loc. Description Loc. 00 20 01 21 02 22 03 23 04 24 05 25 06 26 07 27 08 28 09 29 0A 2A 0B 2B 0C 2C 0D 2D 0E 2E 0F 2F 10 30 11 31 12 32 13 33 14 34 15 35 16 36 17 37 18 38 19 39 1A 3A 1B 3B 1C 3C 1D 3D 1E 3E 1F 3F 124 www.xilinx.com Description PicoBlaze 8-bit Embedded Microcontroller UG129 (v1.1.