Virtex-4 LX/SX Prototype Platform User Guide UG078 (v1.
R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typographical . . . . . . . . . . . . . . . . .
R 4 www.xilinx.com Virtex-4 LX/SX Prototype Platform UG078 (v1.
R Preface About This Guide This user guide describes the features and operation of the Virtex™-4 prototype platform and describes how to configure chains of FPGAs and serial PROMs. Guide Contents This manual contains one chapter: • “Virtex-4 LX/SX Prototype Platform” Additional Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature/index.htm.
R Preface: About This Guide Convention Meaning or Use Example Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information. Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. Square brackets [ ] An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.
R Virtex-4 LX/SX Prototype Platform Package Contents • Xilinx Virtex™-4 prototype platform board • User guide • Device vacuum tool • Headers for test points • CD-ROM • One low-voltage, 14-pin, dual-inline package (DIP) crystal oscillator CD-ROM Contents • User guide in PDF format • Example designs ♦ These designs include the Verilog source code, user constraints files (*.ucf), documentation in PDF, and a readme.txt file • Bitstream files (*.
R Introduction Features • Independent power supply jacks for VCCINT, VCCO, and VCCAUX • Selectable VCCO-enable pins for each SelectIO™ bank • Configuration port for use with Parallel Cable III and Parallel Cable IV cables • 32 clock inputs ♦ 4 differential clock pairs ♦ 4 LVTTL-type oscillator sockets ♦ 20 breakout clock pins • Power indicator LEDs • Onboard Platform Flash ISPROM (32 Mb) for configuration • Onboard power supplies for the Platform Flash ISPROM • JTAG port for reprogramm
R Introduction Figure 1 shows a block diagram of the board.
R Detailed Description Detailed Description The Virtex-4 prototype platform board is shown in Figure 2. Each feature is detailed in the numbered sections that follow. 6a 6c 4 1 11 10 13 3 2 19 9 13 13 12 8 13 7 14 16 5 15 6b 6d Figure 2: 17 18 UG078_02_101904 Detailed Description of Virtex-4 LX/SX Prototype Platform Components 1. Power Switch The board has an onboard power supply and an ON|OFF power switch.
R Detailed Description Table 1: Voltage Ranges Label Maximum Voltage Maximum Current VCCINT 1.2V 1A VCCO 3.3V 2A VCCAUX 2.5V 1.5A VCC 3.3V 2A VCC1V8 1.8V 1A AVCC 2.5V 25 mA Off Position In the OFF position, the power switch disables all modes of powering the DUT. Power Enable Jumpers For each power supply there are headers marked SUPPLY on one side and JACK on the other side.
R Detailed Description 3. Configuration Ports These headers can be used to connect a Parallel Cable III or Parallel Cable IV cable to the board (see Table 2) and support all Virtex-4 device configuration modes. See Table 3 for connecting the cables to the configuration ports and Figure 3 for setting up the JTAG chain on the board.
R Detailed Description 4. JTAG Chain Jumper J17 provides the ability to have the Virtex-4 in the JTAG chain or remove it from the JTAG chain. Note: The Virtex-4 device must not be in the socket when detecting the ISPROM in the chain. 5. JTAG Termination Jumper The DUT TDO pin can be jumpered to the TDO TERM pin or the downstream TDO pin.
R Detailed Description 6a. Upstream System ACE Interface Connector The upstream System ACE interface connector, as shown in Figure 4, can be used to configure the DUT. Any JTAG configuration stream can source this connector. For example, a System ACE controller with a CompactFlash card can be used to generate very large JTAG streams for configuring multiple Virtex-4 prototype platforms using the downstream System ACE interface connector.
R Detailed Description 6c. Upstream Interface Connector The upstream interface connector, as shown in Figure 6, is used to configure the DUT in select map or slave-serial mode. This connector can be sourced by a downstream interface connector of another prototype platform board.
R Detailed Description 6d. Downstream Interface Connector The downstream interface connector, as shown in Figure 7, passes serial configuration information to the DUT in the downstream prototype platform board.
R Detailed Description 10. Oscillator Sockets The board has four crystal oscillator sockets, all wired for standard LVTTL-type oscillators. These sockets connect to the DUT clock pads as shown in Table 4 and Table 5. Onboard termination resistors can be changed by the user. The oscillator sockets accept both halfand full-sized oscillators and are powered by the DUT VCCO power supply.
R Detailed Description 11. Differential Clock Inputs In addition to the oscillator sockets, there are eight 50Ω SMA connectors that allow connection to an external function generator. These connect to the DUT clock pads as shown in Table 6 and Table 7. They can also be used as differential clock inputs. The differential clock pairings (DIFFERENTIAL PAIRS) are as shown in the tables.
R Detailed Description 12. DUT Socket The DUT socket contains the user FPGA, referred to as the device under test (DUT). The DUT must be oriented using the P1 indicator on the board. Caution! Failure to insert the device to the proper orientation can damage the device. To avoid pin damage, always use the vacuum tool provided when inserting or removing the Virtex-4 device. When using BGA packages, do not apply pressure to the device while activating the socket.
R Detailed Description Table 9: Breakout Clock Pin Connections for FF1148 and FF1513 FF1148 Breakout Area Label 20 Clock Name FF1513 Pin Number Clock Name Pin Number IO_L4P_GC_LC_3 E13 IO_L4P_GC_LC_3 J21 IO_L4N_GC_VREF_LC_3 E17 IO_L4N_GC_VREF_LC_3 J20 IO_L5P_GC_LC_3 K18 IO_L5P_GC_LC_3 M21 IO_L5N_GC_LC_3 K17 IO_L5N_GC_LC_3 M20 IO_L6P_GC_LC_3 E16 IO_L6P_GC_LC_3 L20 IO_L6N_GC_LC_3 F16 IO_L6N_GC_LC_3 L19 IO_L7P_GC_LC_3 K19 IO_L7P_GC_LC_3 P22 IO_L7N_GC_LC_3 J19 IO_L7N_GC_L
R Detailed Description 14. User LEDs (Active-High) There are 16 active-high user LEDs on the board. Before configuration, the LEDs reflect the status of the configuration mode pins. During configuration, the LEDs are in a highimpedance condition. After configuration, the LEDs are available to the user and reflect the status of pins D0-D7 and D24-D31 (corresponding to LED 0- LED 15). The LED assignments are shown in Table 10.
R Detailed Description 15. PROGRAM Switch The active-low PROGRAM switch, when pressed, grounds the program pin on the DUT. 16. RESET Switch (Active-Low) The RESET switch connects to a standard I/O pin on the DUT, allowing the user, after configuration, to reset the logic within the DUT. When pressed, this switch grounds the pin. Table 11 shows the INIT pin locations for the available DUT package types.
