Inc. Bus Analyzer Product Specification

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DS619 (v1.0) September 17, 2007 www.xilinx.com

Product Specification 1

PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.

Introduction

The ChipScope™ PLB IBA core is a specialized Bus

Analyzer core designed to debug embedded systems that

contain the IBM CoreConnect™ Processor Local Bus (PLB)

version 4.6. The ChipScope PLB46 IBA core in EDK is

based on a Tcl script that generates an HDL wrapper to the

PLB IBA and calls the ChipScope Core Generator to

generate the netlist based on user parameters.

Features

The ChipScope PLBv46 IBA is a soft IP core designed for

Xilinx® FPGAs and contains the following features:

• Probes the master, slave, arbiter, and error status

signals of the PLBv46 bus

• Probes the PLBv46 OR'ed slave signals

• Automatically adjusts ports to the PLBv46 bus width

• Separates master, slave, and error status signals into

independent match units which can be enabled or

disabled by a design parameter

• Allows independent enabling or disabling of probed

master, slave, and error status signals for data capture

• Supports trigger port customization by a design

parameter

• Supports match unit type customization for each trigger

port by a design parameter

• Supports sample depths from 1024-131,072 on

Virtex™-5 Devices selectable by a design parameter

• Can probe as few as 1 signals and as many as 1115

signals on a Virtex-5 device

• Provides a separate input bus to allow a user-defined

input debug port

• Supports a trigger output indicator pin that can be sent

off chip or to other cores

ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)

DS619 (v1.0) September 17, 2007 Product Specification

LogiCORE™ Facts

Core Specifics

Supported Device

Family

Virtex-E, Virtex, Spartan™-3A DSP,

Spartan-3AN, Spartan-3A, Spartan-3E,

Spartan-3, Spartan-IIE, Spartan-II, Virtex-5

LX, Virtex-5 LXT Virtex-5 SXT, Virtex-4 FX,

Virtex-4 LX, Virtex-4 SX, Virtex-II Pro,

Virtex-II, Virtex-II Pro, Virtex-4

Version of Core chipscope_plb46_iba V1.00a

Resources Used

Min Max

Slices

LUTs

FFs

Block RAMs

Provided with Core

Documentation Product Specification

Design File

Formats

VHDL/EDIF

Constraints File N/A

Verification N/A

Instantiation

Templa t e

N/A

Reference Designs None

Design Tool Requirements

Xilinx

Implementation

Tools

ISE™ 9.2i or later

Verification ChipScope Pro 9.2i or later

Simulation Not supported in simulation

Synthesis XST

Support

Provided by Xilinx, Inc.

Summary of content (10 pages)

PAGE 1
I R < B L ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) DS619 (v1.0) September 17, 2007 Product Specification Introduction LogiCORE™ Facts The ChipScope™ PLB IBA core is a specialized Bus Analyzer core designed to debug embedded systems that contain the IBM CoreConnect™ Processor Local Bus (PLB) version 4.6. The ChipScope PLB46 IBA core in EDK is based on a Tcl script that generates an HDL wrapper to the PLB IBA and calls the ChipScope Core Generator to generate the netlist based on user parameters.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) enabled and defined with unique C_MU_xx_TYPE pattern match units. a user to look for multiple occurrences of the match event. This counter width is controllable through the C_MU_xx_CNT_W parameter (xx is a place holder for 1-13). When this parameter is set to 0 only 1 occurrence is counted, otherwise the match event count is limited by the width of this parameter. The 6a and 6b match units are used for the slave side interface.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Generic Feature/Description Parameter Name Allowable Values Default Value VHDL Type G8 PLB Address Bus Width C_PLBV46_AWIDTH 32 32 Integer G9 PLB Data Bus Width C_PLBV46_DWIDTH 32,64,128 64 Integer IBA Storage Options and Trig Out G10 Number of data samples captured for every C_NUM_DATA_SAMPLES trigger match. Note that the range of acceptable values depends on the C_FAMILY value.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Generic Feature/Description Parameter Name Allowable Values Default Value VHDL Type G30 0=basic, 1=basic w/ edges, 2=extended, 3= extended w/edges, 4=range, 5=range w/edges C_MU_3_TYPE_ADDR 0,1,2,3,4,5 0 Integer G31 Match unit counter width. 0 means do not use C_MU_3_CNT_W_ADDR 0,1-32 0 Integer G32 1=Enable storing MU 3 signals in the data sample storage buffer.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Generic G46 Feature/Description Parameter Name 1=Enable storing MU 6 signals in the data sample storage buffer. 0=Disable C_MU_6_EN_STORE_SLV_ CTL_BUS Allowable Values Default Value VHDL Type 0,1 1 Integer C_USE_MU_6A_SLV_CTL or C_USE_MU_6B_SLV_SZ_WADDR must be 1 in order to store.
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R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) Table 2: IBA_PLBv46 Design Parameters (Continued) Generic Feature/Description Parameter Name Allowable Values Default Value VHDL Type PLB Master Control Bus G63 Use Master Control Signals C_USE_MU_11_MSTR_CTL 1,0 0 Integer G64 Number of match units to use C_MU_11_NUM_MSTR_CTL 1,2 1 Integer G65 0=basic, 1=basic w/ edges C_MU_11_TYPE_MSTR_CTL 0,1 0 Integer G66 Match unit counter width.
PAGE 10
R ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a) assigned for this match group. When multiple match units are available, sequences of a match unit group can be detected. For example, in MU_2, a trigger sequence could be created to look for PLB_PAValid=1 followed by a rising edge on PLB_SaddrAck. For this specific trigger event the first match unit of MU_2 would be set to PLB_PAValid=1 and the second to PLB_SaddrAck=R. Allowable Parameter Combinations All parameters are independent of each other.