User manual

12 www.xilinx.com Virtex-II Prototype Platform
1-800-255-7778 UG015 / PN0401974 (v1.1) January 14, 2003
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• Four global clock (GCLK) inputs
♦ two 50Ω SMB connectors
♦ two LVTTL-type oscillator sockets
• On-board programmable oscillator
• Selectable on-board clock frequency (from 25 MHz to 90 MHz)
• Power indicator LED
• 44-pin, VQFP PROM socket for any configuration mode
• JTAG port for reprogramming the XC17Vxx and XC18Vxx series reconfigurable
PROMs and the User FPGA (DUT)
• Upstream and downstream System ACE and Configuration Interface connectors
• On-board battery holder
The kit contains headers that can be soldered to the breakout area, if desired. These
headers are useful with certain types of oscilloscope probes for either connecting function
generators or wiring pins to the prototype area.
The Virtex-II Prototype Platform board (referred to as “the board”) contains two FPGAs, a
Device Under Test (DUT) FPGA and a Service FPGA.
The DUT can be configured either by a PROM in the User PROM socket or by the PROM
Daughter Card Interface header. The header allows the PROM to be substituted with a
daughter board, permitting daisy-chaining of PROMs and experimentation with other
configuration methods. (Consult the Xilinx data book,
http://www.xilinx.com/partinfo/databook.htm
, for selecting the appropriate PROM
device for each particular Virtex-II device.)
In addition to the User PROM socket and the PROM Daughter Card Interface header, there
are two upstream connectors and two downstream connectors. The upstream connectors
can be connected to configure the DUT using any configuration source, such as a
MultiLINX cable, Parallel Cable III, Parallel Cable IV, or System ACE. The downstream
connectors can be used to connect to another board in a chain.
The Service FPGA is a switch matrix used to control the routing of all of the configuration
signals on the board. This enables simple rotary switches (rather than jumpers) to control
the board, minimizing training and errors. An XC18V01 serial PROM configures the
Service FPGA. Neither this PROM nor the Service FPGA are part of the user configuration
chain. Only the DUT and its related configuration PROM are part of the configuration
chain.
Warning!
Do not use the JTAG Interface Service PROM and FPGA header. This can cause the
board to malfunction. This header is for internal use only.