User manual

Virtex-II Prototype Platform www.xilinx.com 13
UG015 / PN0401974 (v1.1) January 14, 2003 1-800-255-7778
Introduction
R
Figure 1 shows a block diagram of the board.
Figure 1: Virtex-II Prototype Platform Block Diagram
User Reset
VBATT
Done
LED
Init
LED
Program
Virtex-II
DUT
SPROM
(VQ44 Socket)
LVCMOS2 OSC LVCMOS2 OSC SMB
Header for PROM
Daughter Board
To Upstream Board
JTAG
Clock Enable Dip Switch
CLK_DOUBLE
Clock
Generator
Frequency Select
25-90 MHz
JTAG Control *1
Configuration Mode *2
Chip Select
Select Map
Service FPGA
JTAG
TCK, TMS, TDI, TDO
Parallel/Serial
D0-D7, CCLK
Test Points
on All Pins
To Downstream Board
*1: JTAG Control
0: FPGA
1: PROM
2: FPGA→PROM
3: PROM→FPGA
4: FEEDTHROUGH
*2: Configuration Mode
JTAG Select Map
Data/Control
CCLK
JTAG
MODE
GCLK
LEDs
0: MASTER SERIAL (PROM)
1: MASTER SERIAL (UPSTREAM)
2: MASTER SELECT MAP (PROM)
3: MASTER SELECT MAP (UPSTREAM)
4: SLAVE SERIAL
5: JTAG
6: SELECT MAP
7: EXTERNAL
Power Bus and Switches
3PDT
Switch
On-Off-On
VCC
VCCO
Local Power
To Downstream Board
VCCI
To Upstream Board
3.3V Jack
9V Jack
VCC Jack
VCCO Jack
VCCI Jack
1.5V
3.3V
3.3V
HSWAP_EN (ON/OFF)
UG015_01_052101