User manual

28 www.xilinx.com Virtex-II Prototype Platform
1-800-255-7778 UG015 / PN0401974 (v1.1) January 14, 2003
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User Programmable Pins
Table 14 shows the user hardware that corresponds to available DUT package types.
Table 15 shows the clock pins and corresponding I/Os.
Table 14: User Hardware and Corresponding I/Os
Pin Number For Package Type
Label FG256 FG456 FG676 FF1152
RESET (INIT) T13 AA19 AC21 AL5
D0/LED 0 P13 V18 Y20 AG10
D1/LED 1 R13 V17 Y19 AH11
D2/LED 2 N12 W18 AA20 AK7
D3/LED 3 P12 Y18 AB20 AK8
D4/LED 4 P5 Y5 AB7 AK28
D5/LED 5 N5 W5 AA7 AL29
D6/LED 6 R4 AB4 AD6 AG24
D7/LED 7 P4 AA4 AC6 AG25
Note: Refer to the readme.txt file for implementation of these user pins.
Table 15: Clock Pins and Corresponding I/Os
FG256 FG456 FG676 FF1152
Clock Pins
Clock
Name
Pin
Number
Clock
Name
Pin
Number
Clock
Name
Pin
Number
Clock
Name
Pin
Number
CLOCK ENABLE 0 GCLK1S R9 GCLK1S AA12 GCLK1S AC14 GCLK6P AK19
CLOCK ENABLE 1 GCLK6P R8 GCLK6P Y11 GCLK6P AB13 GCLK1S AK16
CLOCK ENABLE 2 GCLK5S P8 GCLK5S W11 GCLK5S AA13 GCLK2P AG17
CLOCK ENABLE 3 GCLK4P N8 GCLK4P V11 GCLK4P Y13 GCLK3S AF17
CLOCK ENABLE 4 GCLK7P D8 GCLK7P D11 GCLK7P F13 GCLK0S H16
CLOCK ENABLE 5 GCLK6S C8 GCLK6S C11 GCLK6S E13 GCLK1P H17
CLOCK ENABLE 6 GCLK5P B8 GCLK5P B11 GCLK5P D13 GCLK2S E16
CLOCK ENABLE 7 GCLK2S B9 GCLK2S F13 GCLK2S H15 GCLK5P E19
OSC Socket Top GCLK0S D9 GCLK0S D12 GCLK0S F14 GCLK7P K18
OSC Socket Bottom GCLK3S N9 GCLK3S W12 GCLK3S AA14 GCLK4P AF18
SMB Top GCLK1P C9 GCLK1P E12 GCLK1P G14 GCLK6S J18
SMB Bottom GCLK2P P9 GCLK2P Y12 GCLK2P AB14 GCLK5S AG18
Breakout Area 1 GCLK3P A9 GCLK3P F12 GCLK3P H14 GCLK4S E18
Breakout Area 2 GCLK4S A8 GCLK4S A11 GCLK4S C13 GCLK3P E17