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ML361 Virtex-II Pro

DDR400/PC3200 Memory

Board User Guide

UG060 (v1.2) November 8, 2007

Summary of content (90 pages)

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ML361 Virtex-II Pro DDR400/PC3200 Memory Board User Guide UG060 (v1.
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R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
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Table of Contents Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Resources . . . . . . . . . . . . .
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R FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 3: Electrical Requirements Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Schedule of Figures Chapter 1: Introduction Figure 1-1: Simplified Block Diagram of Memory Board Interfaces . . . . . . . . . . . . . . . . . 11 Chapter 2: Architecture Figure 2-1: ML361 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 3: Electrical Requirements Chapter 4: Signal Integrity Recommendations and Simulations Figure 4-1: Data Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R Figure 4-29: Data Signals from Memory to FPGA (55Ω Impedance) . . . . . . . . . . . . . . . . . 59 Figure 4-30: Clock Signals with 45Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 4-31: Clock Signals with 55Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 4-32: Address/Control Signals with 45Ω Impedance Measured at First DDR Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Schedule of Tables Chapter 1: Introduction Chapter 2: Architecture Table 2-1: GPIO Header 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2-2: GPIO Header 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2-3: DIP Switch Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2-4: Display 1 . . . . . . . . . . . .
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R 8 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R Preface About This Guide This document describes the design of the ML361 Virtex-II Pro™ DDR400/PC3200 Memory Board, which connects a Virtex-II Pro FPGA to DDR memories. Guide Contents This manual contains the following chapters: • Chapter 1, “Introduction,” describes the purpose of the ML361 board and provides its key features. • Chapter 2, “Architecture,” provides a block diagram of the memory board and describes the key components.
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R Preface: About This Guide Resource Data Sheets Description/URL Device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp Problem Solvers Interactive tools that allow you to troubleshoot your design issues http://support.xilinx.com/support/troubleshoot/psolvers.
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R Chapter 1 Introduction Overview The ML361 Virtex-II Pro DDR400/PC3200 Memory Board provides a communications platform between a Virtex-II Pro FPGA and high-speed double-data-rate (DDR) memories with operating speeds up to 200 MHz.
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R Chapter 1: Introduction The ML361 demonstrates a 64-/72-bit interface to a 128 MByte, 200 MHz DDR SDRAM DIMM, a 72-bit interface to five 256 Mbit, 200 MHz DDR SDRAM components, and an additional 8-bit interface to a 256 Mbit, 200 MHz DDR SDRAM component on one of the top banks.
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R Chapter 2 Architecture This chapter provides functional descriptions of the major blocks within the ML361 board design. For more detailed information on the design, refer to the schematics, which are located at http://www.xilinx.com/bvdocs/userguides/ug060.zip. ML361 Board Block Diagram Figure 2-1 shows a block diagram of the ML361 board. Refer to the following section for additional information on the major blocks.
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R Chapter 2: Architecture Block Descriptions This section describes the major blocks of the ML361 board. FPGA The ML361 uses a Xilinx XC2VP20FF1152C-6 Virtex-II Pro device. This device is packaged in a 1152-pin BGA package with a -6 speed grade. Refer to Appendix B, “FPGA Pinout,”for a complete pinout of the Virtex-II Pro device. Memories The ML361 board supports two types of memories: DDR SDRAM DIMM and DDR SDRAM.
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R Block Descriptions 166 MHz LVDS Test Clock The LVDS test clock is a Pletronics SM7745DW-100.0M clock oscillator with a single-ended output. This oscillator runs at 166 MHz ± 50 PPM with an operating voltage of 2.5 V ± 5%. FPGA pins E17 and D17 in Bank 1 serve as the CLK_166_LVDSP and CLK_166_LVDSN inputs, respectively. SMA Clock Two SMA connectors are provided for the input of an off-board differential clock.
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R Chapter 2: Architecture II Table 2-2: GPIO Header 2 GPIO Pin # FPGA I/O Pin G08 D30 G09 D29 G10 K23 G11 J23 G12 H22 G13 G22 G14 D26 G15 C26 DIP Switch One eight-position DIP switch is connected to the FPGA I/Os as shown in Table 2-3. These switches can be used to externally pull up or pull down any signal on the FPGA.
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R Block Descriptions Table 2-4: Table 2-5: Display 1 DIsplay Input FPGA I/O Pin # Display1F C24 Display1G D24 Display 2 DIsplay Input FPGA I/O Pin # Display2A D20 Display2B D21 Display2C F20 Display2D G20 Display2E K19 Display2F L19 Display2G C22 LEDs Four green LEDs connect to the FPGA I/Os as indicated in Table 2-6. The LEDs are active Low.
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R Chapter 2: Architecture Power Power Distribution The ML361 board uses a 5V input voltage source to generate all the on-board voltages (1.3V, 1.5V, 2.6V, and 3.3V, and the 2.5V for the MGTs) Input Voltage The input voltage is specified at 5 V @ 6.5 A. The recommended power supply is a CUI Inc. DTS050650UTC-PSP-SZ. The jack used is a 4-pin barrel jack, CUI stack PJ-002A-SMT. The slide switch is a CW Industries G1123-0009. This power input has alternate input solder pads. 3.
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R Block Descriptions PROMs The ML361 board contains XCF04S PROMs that can be used to program the Virtex-II Pro FPGA. The PROM operates with a 3.3 V core voltage and a 2.5 V I/O voltage. ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 www.xilinx.
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R Chapter 2: Architecture 20 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R Chapter 3 Electrical Requirements Power Consumption Table 3-1 lists the operating voltages, maximum currents, and power consumption used by the ML361 board devices. Refer to Appendix A, “Related Documentation,” for more information on the source material. Table 3-1: ML361 Power Consumption Device Quantity Voltage (V) Current (mA) Power (W) 1 5 6500 32.5 Source Total Available Power Power Supply FPGA Power (Based on Design) FPGA (XC2VP20-6 FF1152) 1 6.
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R Chapter 3: Electrical Requirements FPGA Internal Power Budget The following tables show the power consumption values inside the FPGA based on the complete DDR design. These results are derived using the Xilinx Power Estimator tool. Block Select RAM, Block Multiplier, Processor, and MGT Power tables are not included in this section as they are not used in this application.
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R Table 3-5: FPGA Internal Power Budget CLB Logic Power Name Total Frequency Number (MHz) of CLB Slices Total Average Total Number Total Number Number of Toggle of Shift of Select Flip/Flop or Rate Register LUTs RAM LUTs Latches % Amount of Routing Used VCCINT Subtotal (mW) User Module 1 200 2597 2603 0 1088 40% High 2439 User Module 2 0 0 0 0 0 0% Low 0 User Module 3 0 0 0 0 0 0% Low 0 User Module 4 0 0 0 0 0 0% Low 0 User Module 5 0 0 0 0 0 0% Low 0 Us
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R Chapter 3: Electrical Requirements Table 3-7: Input/Output Power Total Number of Outputs Average IOB Toggle Rate % Average Output Enable Rate % Average VCCINT VCCO IOB Output Subtotal Subtotal Load Registers (mW) (mW) (pF) Frequency (MHz) I/O Standard Type Total Number of Inputs Jpheader 200 LVCMOS25_12 0 16 25% 100% 0 SDR 2 30 ddr_dq 200 SSTL2_II 138 138 80% 50% 5 DDR 462 877 ddr_dqs 2000 SSTL2_II 18 18 80% 50% 5 DDR 335 363 ddr_address 200 SSTL2_II 0 15 25
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R Chapter 4 Signal Integrity Recommendations and Simulations This chapter provides the following information: • Summary of the termination schemes for various signals (“Termination and Transmission Line Summaries,” page 25) • Summary of the observed duty cycles for all signals in the IBIS simulations (“Duty Cycle Summary,” page 27) • IBIS simulations and duty cycle measurements (“IBIS Simulations,” page 29) Termination and Transmission Line Summaries Table 4-1 summarizes the terminations for the fiv
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R Chapter 4: Signal Integrity Recommendations and Simulations Table 4-2: No. DIMM Terminations Drivers at the FPGA Signal 4 3 pairs of Clocks (CK, CKn) 5 Address (A, BA) 6 Control (RASn, CASn, WEn, CSn, CKE and others) SSTL2_C2 Termination at FPGA Termination at Memory 50Ω pull-up to 1.3 V 50Ω pull-up to 1.
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R Duty Cycle Summary • There is a total of 4.9 inches of trace from the FPGA to the last component assuming the DDR memory components are 0.6 inch apart. Microstrip is used to model the transmission lines for the first DDR component. All other DDR components use Buried Microstrip to model the transmission lines.
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R Chapter 4: Signal Integrity Recommendations and Simulations Table 4-3: Duty Cycle Summary No. 3 4 5 28 Signal Address/control Clock Data DDR Component Middle component Last component Last component Case Duty Cycle Measured at Memory(%) Duty Cycle Measured at FPGA (%) Typical 49.23/51.49 NA Slow weak 49.22/50.64 NA Fast strong 48.94/51.2 NA Typical 48.1/52.04 NA Slow weak 48.66/51.48 NA Fast strong 48.1/51.48 NA Typical 47.24/52.62 48.64/51.78 Slow weak 47.52/52.
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R IBIS Simulations IBIS Simulations This section summarizes various simulations run on the Memory Board using IBIS. It defines the test conditions and provides color-coded screen captures of the results. The resulting signal duty cycles are given also. The simulations have been divided into the following categories: 1. Data Signal Simulations a. b. 2.
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R Chapter 4: Signal Integrity Recommendations and Simulations c. Address and Control Signals - Address and Control Signals with 45Ω Transmission Lines Measured at First DDR Component (Typical) - Address and Control Signals with 55Ω Transmission Lines Measured at First DDR Component (Typical) Notes on the Simulation Results The provided screen captures show the results of each simulation.
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R IBIS Simulations Data Signal Simulations All data signal simulations below have the following test conditions for typical, slow weak, and fast strong cases: • Topology for data signals: 50Ω Transmission lines • At memory (yellow signal): 50Ω parallel termination pulled up to 1.3 V • At FPGA (red signal): 50Ω parallel termination pulled up to 1.3 V (SSTL2C2 drivers at FPGA). Figure 4-1 shows the data signal terminations.
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R Chapter 4: Signal Integrity Recommendations and Simulations Data Signals from the FPGA to Memory (SSTL2_C2 at FPGA) The simulations in this subsection test the data signals from the FPGA to memory. Simulations were performed for the following cases: typical, slow weak, fast strong. An eye diagram is provided also. Typical Case Simulation for Data Signals from the FPGA to the Last DDR Component For the typical case simulation, the resulting duty cycle is 47.24/52.62.
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R IBIS Simulations Slow Weak Corner Case for Data from the FPGA to the Last DDR Component For the slow weak case simulation, the resulting duty cycle is 47.52/52.06. Figure 4-3 shows the simulation screen capture for this case. X-Ref Target - Figure 4-3 ug060_c5_03_091003 Figure 4-3: Data Signal from FPGA to Memory (Slow Weak Case) ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Fast Strong Case for Data Signals from the FPGA to the Last DDR Component For the fast strong case simulation, the resulting duty cycle is 46.4/52.9. Figure 4-4 shows the simulation screen capture for this case. X-Ref Target - Figure 4-4 ug060_c5_04_091003 Figure 4-4: 34 Data Signal from FPGA to Memory (Fast Strong Case) www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Eye Diagram Figure 4-5 shows the eye diagram for the data signals from the FPGA to the last memory component. X-Ref Target - Figure 4-5 ug060_c5_05_091003 Figure 4-5: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Eye Diagram for Data from the FPGA to Last Memory Component www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Data Signals from the Last Memory to the FPGA: Measured at FPGA The simulations in this subsection test the data signals from the last memory to the FPGA. Simulations were performed for the following cases: typical, slow weak, and fast strong. An eye diagram is provided also. Typical Case for Data from the Last DDR Memory Device to the FPGA For the typical case simulation, the resulting duty cycle is 48.64/51.78.
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R IBIS Simulations Slow Weak Corner Case for Data Signals from the Last DDR Memory to the FPGA For the slow weak case simulation, the resulting duty cycle is 49.52/50.64. Figure 4-7 shows the simulation screen capture for this case. X-Ref Target - Figure 4-7 ug060_c5_07_031204 Figure 4-7: Data Signal from Last Memory at FPGA (Slow Weak Corner Case) ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Fast Strong Corner Case for Data from Memory to the FPGA For the fast strong case simulation, the resulting duty cycle is 48.38/51.76. Figure 4-8 shows the simulation screen capture for this case. X-Ref Target - Figure 4-8 ug060_c5_08_031204 Figure 4-8: 38 Data Signal from Memory at FPGA (Fast Strong Corner Case) www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Eye Diagram for Data Signal Measured at the FPGA Figure 4-9 shows the eye diagram for the data signals from the FPGA to the last memory component. X-Ref Target - Figure 4-9 ug060_c5_09_031504 Figure 4-9: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Eye Diagram for Data at the FPGA to the Last Memory Component www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Clock Signal Simulations The simulations in this subsection test the unidirectional clock signals from the FPGA to memory. Simulations were performed for the following cases: typical, slow weak, and fast strong. An eye diagram is provided also.
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R IBIS Simulations Typical Case for Clock Signals For the typical case simulation, the resulting duty cycle is 48.1/52.04. Figure 4-11 shows the simulation screen capture for this case. X-Ref Target - Figure 4-11 ug060_c5_12_091003 Figure 4-11: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Clock Signal from FPGA to Memory (Typical Case) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Slow Weak Case for Clock Signals For the slow weak case simulation, the resulting duty cycle is 48.66/51.48. Figure 4-12 shows the simulation screen capture for this case. X-Ref Target - Figure 4-12 ug060_c5_13_091003 Figure 4-12: 42 Clock Signal from FPGA to Memory (Slow Weak Case) www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Fast Strong Case for Clock Signals For the fast strong case simulation, the resulting duty cycle is 48.1/51.48. Figure 4-13 shows the simulation screen capture for this case. X-Ref Target - Figure 4-13 ug060_c5_11_091003 Figure 4-13: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Clock Signal from FPGA to Memory (Fast Strong Case) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Eye Diagram of Clock Signals at Memory Figure 4-14 shows the eye diagram for the clock signals at memory. X-Ref Target - Figure 4-14 ug060_c5_14_091003 Figure 4-14: 44 Eye Diagram for Clock at Memory www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Address and Control Signal Simulations The simulations in this subsection test the unidirectional address and control signals from the FPGA to five DDR memory components. Simulations were performed on the first, middle, and last DDR memory component for the following cases: typical, slow weak, and fast strong.
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R Chapter 4: Signal Integrity Recommendations and Simulations Typical Case Simulation at All Memory Components Figure 4-16 shows the simulation screen capture for the typical case for all memory components. X-Ref Target - Figure 4-16 ug060_c5_16_091003 Figure 4-16: 46 Address/Control Signals for All Memories www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Typical Case Simulation at First DDR Component For the typical case simulation at the first DDR component, the resulting duty cycle is 48.94/51.2. Figure 4-17 shows the simulation screen capture for this case. X-Ref Target - Figure 4-17 ug060_c5_17_091003 Figure 4-17: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Address/Control Signals at First DDR Memory (Typical Case) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Slow Weak Corner Case Simulation at First DDR Component For the slow weak corner case simulation at the first DDR component, the resulting duty cycle is 49.22/51.48. Figure 4-18 shows the simulation screen capture for this case. X-Ref Target - Figure 4-18 ug060_c5_18_091003 Figure 4-18: 48 Address/Control Signals at First DDR Memory (Slow Weak Case) www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Fast Strong Corner Case Simulation at First DDR Component For the fast strong corner case simulation at the first DDR component, the resulting duty cycle is 48.66/51.2. Figure 4-19 shows the simulation screen capture for this case. X-Ref Target - Figure 4-19 ug060_c5_19_091003 Figure 4-19: Address/Control Signals at First DDR Memory (Fast Strong Case) ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Typical Case Simulation at Last DDR Component For the typical case simulation at the last DDR component, the resulting duty cycle is 49.22/50.92. Figure 4-20 shows the simulation screen capture for this case. X-Ref Target - Figure 4-20 ug060_c5_20_091003 Figure 4-20: 50 Address/Control Signals at Last DDR Memory (Typical Case) www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Slow Weak Case Simulation at Last DDR Component For the slow weak case simulation at the last DDR component, the resulting duty cycle is 49.22/50.63. Figure 4-21 shows the simulation screen capture for this case. X-Ref Target - Figure 4-21 ug060_c5_22_091003 Figure 4-21: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Address/Control Signals at Last DDR Memory (Slow Weak Case) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Fast Strong Corner Case Simulation at Last DDR Component For the fast strong corner case simulation at the last DDR component, the resulting duty cycle is 49.22/51.2. Figure 4-22 shows the simulation screen capture for this case. X-Ref Target - Figure 4-22 ug060_c5_21_091003 Figure 4-22: 52 Address/Control Signals at Last DDR Memory (Fast Strong Corner Case) www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Typical Case Simulation at Middle DDR Component For the typical case simulation at the middle DDR component, the resulting duty cycle is 49.23/51.49. Figure 4-23 shows the simulation screen capture for this case. X-Ref Target - Figure 4-23 ug060_c5_23_091003 Figure 4-23: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Address/Control Signals at Middle DDR Memory (Typical Case) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Slow Weak Corner Case Simulation at Middle DDR Component For the slow weak corner case simulation at the middle DDR component, the resulting duty cycle is 49.22/50.64. Figure 4-24 shows the simulation screen capture for this case. X-Ref Target - Figure 4-24 ug060_c5_24_091003 Figure 4-24: 54 Address/Control Signals at Middle DDR Memory (Slow Weak Corner Case) www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R IBIS Simulations Fast Strong Corner Case Simulation at Middle DDR Component For the fast strong corner case simulation at the middle DDR component, the resulting duty cycle is 48.94/51.2. Figure 4-25 shows the simulation screen capture for this case. X-Ref Target - Figure 4-25 ug060_c5_25_091003 Figure 4-25: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Address/Control Signals at Middle DDR Memory (Fast Strong Corner Case) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Simulations with 10% Tolerance on the Transmission Line Impedance These simulations illustrate the typical cases for data, clock, and address and control signals.
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R IBIS Simulations Data Signals from the Last DDR Memory to the FPGA with 55Ω Transmission Line Impedance For the typical case simulation from the last DDR component to the FPGA, the resulting duty cycle is 46.4/52.62. Figure 4-27 shows the simulation screen capture for this case. X-Ref Target - Figure 4-27 ug060_c5_27_031204 Figure 4-27: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Data Signals from Last DDR Memory to FPGA (55Ω Impedance) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Data Signals from FPGA to the Last DDR Memory Component with 45Ω Transmission Line Impedance For the typical case simulation from the FPGA to the last DDR component, the resulting duty cycle is 46.96/53.18. Figure 4-28 shows the simulation screen capture for this case. X-Ref Target - Figure 4-28 ug060_c5_28_091003 Figure 4-28: 58 Data Signals from FPGA to Last DDR Memory (45Ω Impedance) www.xilinx.
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R IBIS Simulations Data Signals from Memory to the FPGA with 55Ω Transmission Line Impedance For the typical case simulation from memory to the FPGA, the resulting duty cycle is 48.66/51.48. Figure 4-29 shows the simulation screen capture for this case. X-Ref Target - Figure 4-29 ug060_c5_29_091003 Figure 4-29: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Data Signals from Memory to FPGA (55Ω Impedance) www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Clock Signals This subsection provides the clock simulation results for the following typical cases: • With 45Ω transmission line impedance • With 55Ω transmission line impedance Clock Signals with 45Ω Transmission Line Impedance For the typical case simulation with a 45Ω transmission line impedance, the resulting duty cycle is 48.66/ 52.04. Figure 4-30 shows the simulation screen capture for this case.
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R IBIS Simulations Clock Signals with 55Ω Transmission Line Impedance For the typical case simulation with a 55Ω transmission line impedance, the resulting duty cycle is 48.1/51.48. Figure 4-31 shows the simulation screen capture for this case. X-Ref Target - Figure 4-31 ug060_c5_31_091003 Figure 4-31: ML361 Virtex-II Pro Memory Board UG060 (v1.2) November 8, 2007 Clock Signals with 55Ω Impedance www.xilinx.
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R Chapter 4: Signal Integrity Recommendations and Simulations Address/Control Signals This subsection provides the address and control simulation results for the following typical cases: • With 45Ω transmission line impedance measured at the first DDR component • With 55Ω transmission line impedance measured at the first DDR component Address and Control Signals with 45Ω Transmission Lines Measured at the First DDR Component For the typical case simulation with a 45Ω transmission line impedance measur
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R IBIS Simulations Address and Control Signals with 55Ω Transmission Lines Measured at the First DDR Component For the typical case simulation with a 55Ω transmission line impedance measured at the first DDR component, the resulting duty cycle is 48.66/51.48. Figure 4-33 shows the simulation screen capture for this case. X-Ref Target - Figure 4-33 ug060_c5_33_091003 Figure 4-33: ML361 Virtex-II Pro Memory Board UG060 (v1.
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Chapter 4: Signal Integrity Recommendations and Simulations 64 www.xilinx.com R ML361 Virtex-II Pro Memory Board UG060 (v1.
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R Chapter 5 Board Layout Guidelines This chapter provides information on decoupling capacitors, ground signals, and PCB layout. Decoupling Guidelines This section lists the decoupling capacitors used with the major components of the ML361 board. Refer to the board schematics for exact placement. Table 5-1 lists the decoupling capacitors for the Virtex-II Pro FPGA. Refer to the Xilinx XAPP623 application note for the methodology.
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R Chapter 5: Board Layout Guidelines Table 5-1: FPGA Decoupling Capacitors (Cont’d) Pin(s) Capacitor Value Distribution Bank 2 7 VREFs used, one capacitor for each VREF VREF 0.039 µF ceramic capacitor, 0402 10V X7R –20/+20% 2 0.22 µF ceramic capacitor, 0603 10V X7R –20/+20% 1 1 µF ceramic capacitor, 0603 6V X7R –20/+20% 1 330 µF solid tantalum capacitor, 6.
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R Table 5-3: Providing Additional Ground Pins DIMM Decoupling Capacitors (Cont’d) Pin(s) Capacitor Value VREF VSS Distribution 0.01 µF ceramic capacitor, 0402 6V X7R –20/+20% 1 VREF to GND 1 VREF to 2.6V 1 GND to 2.6V 0.1 µF ceramic capacitor, 0603 6V X7R –20/+20% 1 VREF to GND 1 VREF to 2.6V 1 GND to 2.6V 0.01 µF ceramic capacitor, 0402 6V X7R –20/+20% 8 0.1 µF ceramic capacitor, 0603 6V X7R –20/+20% 4 330 µF solid tantalum capacitor, 6.
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R Chapter 5: Board Layout Guidelines 68 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R Appendix A Related Documentation This appendix provides references to documents and web pages for components on the ML361 board. • Xilinx, Inc. ♦ Virtex-II Pro X™ Platform FPGAs http://www.xilinx.com/bvdocs/publications/ds083.pdf ♦ Platform Flash In-System Programmable Configuration PROMs http://www.xilinx.com/bvdocs/publications/ds123.pdf • Texas Instruments ♦ PTH05000BAH Regulated Step-down DC/DC 5V to 3.3V @ 5.5A PTH05000FAH Regulated Step-down DC/DC 5V to 1.5V @ 5.5A http://focus.ti.
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R 70 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.
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R Appendix B FPGA Pinout Table B-1 summarizes the pinout of the XC2VP20FF1152-6 FPGA in the ML361 board. The slice coordinates mentioned in Table B-1 refer to the RPM grid coordinates corresponding to the respective I/O pin location. I/O pin names marked as GND refer to unused I/Os that are directly connected to GND. I/O pin names marked as PULLDOWN refer to unused I/Os that are connected to GND through a zero ohm resistor. The 0Ω resistor can be removed to use the corresponding I/O for any test purposes.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names K21 0 IO_L39N_0 GND 5505.04 J21 0 IO_L39P_0 GND 4965.14 F22 0 IO_L43N_0 GPIO00 7541.44 E22 0 IO_L43P_0 GPIO01 8910.89 E25 0 IO_L44N_0 GPIO02 12735.3 D25 0 IO_L44P_0 GPIO03 13832.18 H21 0 IO_L45N_0 GPIO04 6364.26 G21 0 IO_L45P_0/VREF_0 GPIO05 7704.24 D22 0 IO_L46N_0 GPIO06 9988.1 D23 0 IO_L46P_0 GPIO07 11050.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names F18 0 IO_L73P_0 LED4 7223.69 E18 0 IO_L74N_0/GCLK7P GND 8692.96 D18 0 IO_L74P_0/GCLK6S GND 9819.09 J18 0 IO_L75N_0/GCLK5P GND 3858.95 H18 0 IO_L75P_0/GCLK4S GND 5131.43 H17 1 IO_L75N_1/GCLK3P CLK_200_LVDSN 5131.43 J17 1 IO_L75P_1/GCLK2S CLK_200_LVDSP 3858.95 D17 1 IO_L74N_1/GCLK1P CLK_166_LDVSN 10242.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names D12 1 IO_L46N_1 top_address(9) 11050.72 D13 1 IO_L46P_1 top_address(10) 9988.1 G14 1 IO_L45N_1/VREF_1 Vref = 1.3V 7704.24 H14 1 IO_L45P_1 top_address(11) 6364.26 D10 1 IO_L44N_1 top_address(12) 13570.63 E10 1 IO_L44P_1 top_ba(0) 12296.5 E13 1 IO_L43N_1 top_ba(1) 8910.89 F13 1 IO_L43P_1 top_csb 7591.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names E4 2 IO_L03N_2 ddr1_ckn1 6738.57 E3 2 IO_L03P_2 ddr1_ck1 14050.12 E2 2 IO_L04N_2/VREF_2 Vref = 1.3V 15547.77 E1 2 IO_L04P_2 ddr1_dqs0 15132.61 J8 2 IO_L05N_2 ddr1_dm3 6469.14 J7 2 IO_L05P_2 ddr1_dm4 7292.33 F5 2 IO_L06N_2 ddr1_dq0 10666.81 F4 2 IO_L06P_2 ddr1_dq1 11858.77 H2 2 IO_L31N_2 ddr1_dq2 12137.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names M3 2 IO_L43P_2 PULLDOWN 9772.91 P10 2 IO_L44N_2 PULLDOWN 2638.82 P9 2 IO_L44P_2 PULLDOWN 3823 N6 2 IO_L45N_2 ddr1_ckn2 N5 2 IO_L45P_2 ddr1_ck2 7563.61 M1 2 IO_L46N_2/VREF_2 Vref = 1.3V 11667.8 N1 2 IO_L46P_2 ddr1_dqs2 11804.99 P8 2 IO_L47N_2 GND 4770.58 P7 2 IO_L47P_2 GND 5954.75 N4 2 IO_L48N_2 ddr1_dq16 8437.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names T6 2 IO_L60N_2 ddr1_dq29 6031.43 T5 2 IO_L60P_2 ddr1_dq30 7055.3 T4 2 IO_L85N_2 ddr1_dq31 7724.5 T3 2 IO_L85P_2 GND 9056.44 U10 2 IO_L86N_2 ddr1_ba0 2340.31 U9 2 IO_L86P_2 ddr1_ba1 3459.01 U6 2 IO_L87N_2 ddr1_a0 U5 2 IO_L87P_2 ddr1_a1 6851.4 U2 2 IO_L88N_2/VREF_2 Vref = 1.3V 9665.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names Y4 3 IO_L57P_3 ddr1_dq46 8145.63 W7 3 IO_L56N_3 ddr1_dq47 5773.96 W8 3 IO_L56P_3 ddr1_dm5 4826.38 Y6 3 IO_L55N_3 ddr1_a3 5961.45 Y7 3 IO_L55P_3 ddr1_a4 5219.05 AA2 3 IO_L54N_3 ddr1_a5 AB2 3 IO_L54P_3 ddr1_a6 11488.21 W9 3 IO_L53N_3 GND 3619.48 W10 3 IO_L53P_3 ddr1_dqs6 2590.48 AA3 3 IO_L52N_3 GND 9502.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names AC6 3 IO_L40N_3 ddr1_dq60 6521.49 AC7 3 IO_L40P_3 ddr1_dq61 5779.09 AD3 3 IO_L39N_3/VREF_3 Vref = 1.3V 9751.53 AD4 3 IO_L39P_3 ddr1_dq62 9046.71 AB9 3 IO_L38N_3 ddr1_dq63 3854.3 AB10 3 IO_L38P_3 ddr1_dm7 2906.72 AD5 3 IO_L37N_3 ddr1_a10 8126.55 AD6 3 IO_L37P_3 ddr1_a11 8070.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names AL6 4 IO_L01P_4/INIT_B INITn 12205.78 AG9 4 IO_L02N_4/D0 FPGA.DO 6285.75 AH9 4 IO_L02P_4/D1 GND 7853.38 AK6 4 IO_L03N_4/D2 GND 11359.7 AK7 4 IO_L03P_4/D3 GND 11413.02 AF10 4 IO GND 5273.75 AL7 4 IO_L06N_4/VRP_4 M1_even_clk 12583.91 AM7 4 IO_L06P_4/VRN_4 M1_even_ D15 13750.42 AE11 4 IO_L07N_4 M1_even_ D14 3596.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names AE16 4 IO_L49P_4 M1_odd_D6 3442.92 AJ14 4 IO GND 8953.05 AK14 4 IO GND 9556.17 AM14 4 IO_L54N_4 M1_odd_D5 12003.32 AM13 4 IO_L54P_4 M1_odd_D4 12348.43 AF16 4 IO_L55N_4 M1_odd_D3 3887.4 AG16 4 IO_L55P_4 M1_odd_D2 4909.89 AH15 4 IO_L56N_4 M1_odd_D1 7000 AJ15 4 IO_L56P_4 M1_odd_D0 8217.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names AE18 5 IO_L67N_5 GND AD18 5 IO_L67P_5 M2_even_clk AL20 5 IO_L57N_5/VREF_5 M2_even_ D15 AL21 5 IO_L57P_5 M2_even_ D14 AJ20 5 IO_L56N_5 M2_even_ D13 AH20 5 IO_L56P_5 M2_even_ D12 AG19 5 IO_L55N_5 M2_even_ D11 AF19 5 IO_L55P_5 M2_even_ D10 AM22 5 IO_L54N_5 M2_even_D9 AM21 5 IO_L54P_5 M2_even_D8 AK21 5 IO GND AJ21 5 I
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names AK27 5 IO_L09P_5 M2_odd_D3 11420.7 AH25 5 IO_L08N_5 M2_odd_D2 8344.01 AG25 5 IO_L08P_5 M2_odd_D1 7652.81 AF24 5 IO_L07N_5/VREF_5 M2_odd_D0 4532.67 AE24 5 IO_L07P_5 GND 3596.07 AM28 5 IO_L06N_5/VRP_5 GND 13858.11 AL28 5 IO_L06P_5/VRN_5 GND 12527.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names AE31 6 IO_L34N_6 PULLDOWN 9342.05 AD27 6 IO_L35P_6 dimm_dqs1 5651.11 AD28 6 IO_L35N_6 PULLDOWN 6675.24 AF33 6 IO_L36P_6 dimm_dq8 11948.48 AE33 6 IO_L36N_6 dimm_dq9 11537.91 AD29 6 IO_L37P_6 dimm_dq10 8070.54 AD30 6 IO_L37N_6 dimm_dq11 8126.55 AB25 6 IO_L38P_6 dimm_dq12 2906.72 AB26 6 IO_L38N_6 dimm_dq13 3854.
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R Table B-1: FPGA Pinout (Cont’d) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names Internal Script Information Package Flight Times (in microns) AC34 6 IO_L51P_6 PULLDOWN no_pin2 12342.28 AB34 6 IO_L51N_6/VREF_6 Vref = 1.3V 12006.27 AA31 6 IO_L52P_6 PULLDOWN 8801.88 AA32 6 IO_L52N_6 PULLDOWN 9502.86 W25 6 IO_L53P_6 dimm_dqs3 2590.48 W26 6 IO_L53N_6 GND 3619.48 AB33 6 IO_L54P_6 dimm_dq24 11488.21 AA33 6 IO_L54N_6 dimm_dq25 10317.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names U31 7 IO_L90N_7 PULLDOWN U28 7 IO_L89P_7 dimm_rasN U27 7 IO_L89N_7 dimm_casN 4393.22 V33 7 IO_L88P_7 dimm_weN 10394.2 U33 7 IO_L88N_7/VREF_7 Vref = 1.3V 9665.64 U30 7 IO_L87P_7 dimm_rst_dqs_div_out 6851.4 U29 7 IO_L87N_7 dimm_rst_dqs_div_in 5801.93 U26 7 IO_L86P_7 PULLDOWN 3459.01 U25 7 IO_L86N_7 PULLDOWN 2340.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names P33 7 IO_L49P_7 dimm_dq52 10530.82 N33 7 IO_L49N_7 dimm_dq53 10426.76 N32 7 IO_L48P_7 dimm_dq54 9778.21 N31 7 IO_L48N_7 dimm_dq55 8437.77 P28 7 IO_L47P_7 dimm_a0 P27 7 IO_L47N_7 dimm_a1 4770.58 N34 7 IO_L46P_7 dimm_a2 11804.99 M34 7 IO_L46N_7/VREF_7 Vref = 1.3V 11667.8 N30 7 IO_L45P_7 dimm_a3 7563.
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R Table B-1: FPGA Pinout (Cont’d) Package Flight Times (in microns) Pin Numbers Virtex-II Pro Bank Number Package Functional Name I/O Pin Names K30 7 IO_L33N_7 dimm_dq65 8267.43 M26 7 IO_L32P_7 dimm_dq66 4123.3 M25 7 IO_L32N_7 dimm_dq67 3062.48 H34 7 IO_L31P_7 dimm_dq68 13451.41 H33 7 IO_L31N_7 dimm_dq69 12137.04 F31 7 IO_L06P_7 dimm_dq70 11858.77 F30 7 IO_L06N_7 dimm_dq71 10666.81 J28 7 IO_L05P_7 dimm_a10 J27 7 IO_L05N_7 dimm_a11 6469.
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R Table B-1: Pin Numbers FPGA Pinout (Cont’d) Virtex-II Pro Bank Number Package Functional Name I/O Pin Names A9 TXNPAD9 A8 TXPPAD9 A7 RXPPAD9 A6 RXNPAD9 G8 RSVD K9 VBATT K10 TMS TMS J9 TCK TCK H7 DO TDO.FPGA.to.TDO.PORT AE9 CCLK FPGA.
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R 90 www.xilinx.com ML361 Virtex-II Pro Memory Board UG060 (v1.