MicroBlaze Processor Reference Guide www.xilinx.com 105
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
Registers Altered
rD, unless an FP exception is generated, in which case the register is unchanged
ESR[EC]
FSR[IO,DO]
Latency
1 cycle
Note
Theseinstructions areonly available whenthe MicroBlazeparameter C_USE_FPU isset to
1.
Greater-than 100
(rD) 1 (rD) 0 (rD) 0 (rD) 0
FSR[IO] 1
ESR[EC] 00110
Not-equal 101
(rD) 1 (rD) 1 (rD) 0 (rD) 1
Greater-or-equal 110
(rD) 1 (rD) 0 (rD) 1 (rD) 0
FSR[IO] 1
ESR[EC] 00110
Table 4-2: Floating Point Comparison Operation
Comparison Type Operand Relationship
Description OpSel (rB) > (rA) (rB) < (rA) (rB) = (rA) isNaN(rA) or isNaN(rB)