106 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
get
get from fsl interface
Description
MicroBlaze will read from the FSLx interface and place the result in register rD.
The get instruction has four variants.
The blocking versions (when ‘n’ bit is ‘0’) will stall microblaze until the data from the FSL
interface is valid. The non-blocking versions will not stall microblaze and will set carry to
‘0’ if the data was valid and to ‘1’ if the data was invalid. In case of an invalid access the
destination register contents is undefined.
The get and nget instructions expect the control bit from the FSL interface to be ‘0’. If this
is not the case, the instruction will set MSR[FSL_Error] to ‘1’. The cget and ncget
instructions expect the control bitfrom the FSL interface to be ‘1’. If thisis notthe case,the
instruction will set MSR[FSL_Error] to ‘1’.
Pseudocode
(rD) FSLx
if (n = 1) then
MSR[Carry] not (FSLx Exists bit)
if (FSLx Control bit c) then
MSR[FSL_Error] 1
Registers Altered
rD
MSR[FSL_Error]
MSR[Carry]
Latency
2 cycles. For blocking instructions, MicroBlaze will first stall until valid data is available.
Note
For nget and ncget, a rsubc instruction can be used for counting down a index variable
get
rD, FSLx get data from FSL x (blocking)
nget
rD, FSLx get data from FSL x (non-blocking)
cget
rD, FSLx get control from FSL x (blocking)
ncget
rD, FSLx get control from FSL x (non-blocking)
0 1 1 0 1 1 rD 0 0 0 0 0 0 n c 0 0 0 0 0 0 0 0 0 0 FSLx
0 6 11 16 29 31