MicroBlaze Processor Reference Guide www.xilinx.com 107
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
idiv
Integer Divide
Description
The contents of registerrB isdivided bythe contentsof register rAand theresult is placed
into register rD.
If the U bit is set, rA and rB isconsideredunsigned values.If theU bitis clear, rAand rBis
considered signed values
If the value of rA is 0, the divide_by_zerobit in MSR will be set and the value in rD will be
0.
Pseudocode
if (rA) = 0then
(rD) 0
else
(rD) (rB) / (rA)
Registers Altered
rD, unless “Divide by zero” exception is generated, in which case the register is
unchanged
MSR[Divide_By_Zero]
Latency
1 cycle if (rA) = 0, otherwise 32 cycles
Note
This instruction is only valid if MicroBlaze is configured to use a hardware divider
(C_USE_DIV = 1).
idiv
rD, rA, rB divide rB by rA (signed)
idivu
rD, rA, rB divide rB by rA (unsigned)
0 1 0 0 1 0 rD rA rB 0 0 0 0 0 0 0 0 0 U 0
0 6 11 16 21 31