user manual

MicroBlaze Processor Reference Guide www.xilinx.com 11
UG081 (v6.0) June 1, 2006 1-800-255-7778
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Chapter 1
MicroBlaze Architecture
Overview
TheMicroBlazeembeddedprocessorsoftcoreisareducedinstructionsetcomputer(RISC)
optimized for implementation in Xilinx field programmable gate arrays (FPGAs).
Figure 1-1 shows a functional block diagram of the MicroBlaze core.
Features
The MicroBlaze soft core processor is highly configurable, allowing users to select a
specific set of features required by their design.
The processor’s fixed feature set includes:
• Thirty-two 32-bit general purpose registers
• 32-bit instruction word with three operands and two addressing modes
• 32-bit address bus
• Single issue pipeline
Figure 1-1: MicroBlaze Core Block Diagram
DXCL_M
DXCL_S
Data-sideInstruction-side
DOPB
DLMB
IOPB
ILMB
bus interface bus interface
Instruction
Buffer
Program
Counter
Register File
32 X 32b
ALU
Instruction
Decode
Bus
IF
Bus
IF
MFSL 0..7
SFSL 0..7
IXCL_M
IXCL_S
I-Cache
D-Cache
Shift
Barrel Shift
Multiplier
Divider
FPU
Special
Purpose
Registers
Optional MicroBlaze feature