MicroBlaze Processor Reference Guide www.xilinx.com 111
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
lhu
Load Halfword Unsigned
Description
Loads a halfword (16 bits) from the halfword aligned memory location that results from
adding the contents of registers rA and rB. The data is placed in the least significant
halfword of register rD and the most significant halfword in rD is cleared.
Pseudocode
Addr (rA) + (rB)
Addr[31]
0
(rD)[16:31]
Mem(Addr)
(rD)[0:15]
0
Registers Altered
rD, unless unaligned data access exception is generated, in which case the register is
unchanged.
ESR [W]
Latency
1 cycle
lhu rD, rA, rB
1 1 0 0 0 1 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31