112 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
lhui
Load Halfword Unsigned Immediate
Description
Loads a halfword (16 bits) from the halfword aligned memory location that results from
addingthe contents ofregisterrA and thevalue in IMM,sign-extended to 32bits. Thedata
is placed in the least significant halfword of register rD and the most significant halfword
in rD is cleared.
Pseudocode
Addr (rA) + sext(IMM)
Addr[31]
0
(rD)[16:31]
Mem(Addr)
(rD)[0:15]
0
Registers Altered
rD, unless unaligned data access exception is generated, in which case the register is
unchanged.
ESR [W]
Latency
1 cycle
Note
By default, Type BInstructionswill take the16-bit IMM fieldvalue and sign extendit to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
lhui rD, rA, IMM
1 1 1 0 0 1 rD rA IMM
0 6 11 16 31