MicroBlaze Processor Reference Guide www.xilinx.com 113
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
lw
Load Word
Description
Loads a word (32 bits) from the word aligned memory location that results from adding
the contents of registers rA and rB. The data is placed in register rD.
Pseudocode
Addr (rA) + (rB)
Addr[30:31]
00
(rD)
Mem(Addr)
Registers Altered
rD, unless unaligned data access exception is generated, in which case the register is
unchanged.
ESR [W]
Latency
1 cycle
lw rD, rA, rB
1 1 0 0 1 0 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31