114 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
lwi
Load Word Immediate
Description
Loads a word (32 bits) from the word aligned memory location that results from adding
the contentsof register rA and the valueIMM, sign-extended to 32 bits.The data is placed
in register rD.
Pseudocode
Addr (rA) + sext(IMM)
Addr[30:31]
00
(rD)
Mem(Addr)
Registers Altered
rD, unless unaligned data access exception is generated, in which case the register is
unchanged.
ESR [W]
Latency
1 cycle
Note
By default, Type BInstructionswill take the16-bit IMM fieldvalue and sign extendit to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
lwi rD, rA, IMM
1 1 1 0 1 0 rD rA IMM
0 6 11 16 31