MicroBlaze Processor Reference Guide www.xilinx.com 115
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
mfs
Move From Special Purpose Register
Description
Copies the contents of the special purpose register rS into register rD.
Pseudocode
switch (rS):
case 0x0000 :
(rD) PC
case 0x0001 :
(rD) MSR
case 0x0003 :
(rD) EAR
case 0x0005 :
(rD) ESR
case 0x0007 :
(rD) FSR
case 0x000B :
(rD) BTR
case 0x200x :
(rD) PVR[x] (where x = 0 to 11)
default :
(rD) Undefined
Registers Altered
rD
Latency
1 cycle
Note
To refer to special purpose registers in assembly language, use rpc for PC, rmsr for MSR,
rear for EAR, resr for ESR, and rfsr for FSR.
Thevalue readfromMSRmay notincludeeffectsoftheimmediatelyprecedinginstruction
(dependent on pipeline stall behavior). A NOP should be inserted before the MFS
instruction to guarantee correct MSR value.
EAR and ESR are only valid as operands when at least one of the MicroBlaze
C_*_EXCEPTION parameters are set to 1.
FSR is only valid as an operand when the C_USE_FPU and C_FPU_EXCEPTION
parameters are set to 1.
mfs rD, rS
1 0 0 1 0 1 rD 0 0 0 0 0 1 0 rS
0 6 11 16 18 31