MicroBlaze Processor Reference Guide www.xilinx.com 129
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
rtbd
Return from Break
rn from Interrupt
Description
Return from break will branchto the location specifiedby the contentsof rA plus theIMM
field, sign-extended to32 bits.It willalso enablebreaks after execution by clearing the BIP
flag in the MSR.
This instruction always has a delay slot. The instruction following the RTBD is always
executed before the branch target. That delay slot instruction has breaks disabled.
Pseudocode
PC (rA) + sext(IMM)
allow following instruction to complete execution
MSR[BIP] 0
Registers Altered
PC
MSR[BIP]
Latency
2 cycles
Note
Convention is to use general purpose register r16 as rA.
A delay slot must not be used by the following: IMM, branch, or break instructions. This
also applies to instructions causing recoverable exceptions (e.g. unalignement), when
hardware exceptions are enabled. Interrupts and external hardware breaks are deferred
until after the delay slot branch has been completed.
rtbd rA, IMM
1 0 1 1 0 1 1 0 0 1 0 rA IMM
0 6 11 16 31