MicroBlaze Processor Reference Guide www.xilinx.com 137
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
sh
Store Halfword
Description
Stores the contents of the least significant halfword of register rD, into the halfword
aligned memory location that results from adding the contents of registers rA and rB.
Pseudocode
Addr (rA) + (rB)
Addr[31]
0
Mem(Addr)
(rD)[16:31]
Registers Altered
ESR [S]
Latency
1 cycle
sh rD, rA, rB
1 1 0 1 0 1 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31