138 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
shi
Store Halfword Immediate
Description
Stores the contents of the least significant halfword of register rD, into the halfword
alignedmemory location thatresultsfromadding thecontents of registerrAand the value
IMM, sign-extended to 32 bits.
Pseudocode
Addr (rA) + sext(IMM)
Addr[31]
0
Mem(Addr)
← (rD)[16:31]
Registers Altered
ESR [S]
Latency
1 cycle
Note
By default, Type BInstructionswill take the16-bit IMM fieldvalue and sign extendit to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
shi rD, rA, IMM
1 1 1 1 0 1 rD rA IMM
0 6 11 16 31