MicroBlaze Processor Reference Guide www.xilinx.com 139
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
sra
Shift Right Arithmetic
Description
Shifts arithmetically thecontents ofregisterrA, one bitto theright, and placesthe result in
rD. The most significant bit of rA (i.e. the sign bit) placed in the most significant bit of rD.
The least significant bit coming out of the shift chain is placed in the Carry flag.
Pseudocode
(rD)[0] (rA)[0]
(rD)[1:31]
(rA)[0:30]
MSR[C]
(rA)[31]
Registers Altered
rD
MSR[C]
Latency
1 cycle
sra rD, rA
1 0 0 1 0 0 rD rA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 6 11 16 31