MicroBlaze Processor Reference Guide www.xilinx.com 143
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
swi
Store Word Immediate
Description
Storesthe contentsof register rD, into the word alignedmemory locationthat resultsfrom
adding the contents of registers rA and the value IMM, sign-extended to 32 bits.
Pseudocode
Addr (rA) + sext(IMM)
Addr[30:31]
00
Mem(Addr)
(rD)[0:31]
Register Altered
ESR [S]
Latency
1 cycle
Note
By default, Type BInstructionswill take the16-bit IMM fieldvalue and sign extendit to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
swi rD, rA, IMM
1 1 1 1 1 0 rD rA IMM
0 6 11 16 31