146 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
xor
Logical Exclusive OR
Description
The contents of register rA are XORed with the contents of register rB; the result is placed
into register rD.
Pseudocode
(rD) (rA) (rB)
Registers Altered
rD
Latency
1 cycle
xor rD, rA, rB
1 0 0 0 1 0 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31