16 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 1: MicroBlaze Architecture
R
ADDIKC Rd,Ra,Imm 001110 Rd Ra Imm Rd := s(Imm) + Ra + C
RSUBIKC Rd,Ra,Imm 001111 Rd Ra Imm Rd := s(Imm) +
Ra + C
MUL Rd,Ra,Rb 010000 Rd Ra Rb 00000000000 Rd := Ra * Rb
BSRL Rd,Ra,Rb 010001 Rd Ra Rb 00000000000 Rd : = 0 & (Ra >> Rb)
BSRA Rd,Ra,Rb 010001 Rd Ra Rb 01000000000 Rd := s(Ra >> Rb)
BSLL Rd,Ra,Rb 010001 Rd Ra Rb 10000000000 Rd := (Ra << Rb) & 0
MULI Rd,Ra,Imm 011000 Rd Ra Imm Rd := Ra * s(Imm)
BSRLI Rd,Ra,Imm 011001 Rd Ra 00000000000 &
Imm5
Rd : = 0 & (Ra >> Imm5)
BSRAI Rd,Ra,Imm 011001 Rd Ra 00000010000 &
Imm5
Rd := s(Ra >> Imm5)
BSLLI Rd,Ra,Imm 011001 Rd Ra 00000100000 &
Imm5
Rd := (Ra << Imm5) & 0
IDIV Rd,Ra,Rb 010010 Rd Ra Rb 00000000000 Rd := Rb/Ra
IDIVU Rd,Ra,Rb 010010 Rd Ra Rb 00000000010 Rd := Rb/Ra, unsigned
FADD Rd,Ra,Rb 010110 Rd Ra Rb 00000000000 Rd := Rb+Ra, float
1
FRSUB Rd,Ra,Rb 010110 Rd Ra Rb 00010000000 Rd := Rb-Ra, float
1
FMUL Rd,Ra,Rb 010110 Rd Ra Rb 00100000000 Rd := Rb*Ra, float
1
FDIV Rd,Ra,Rb 010110 Rd Ra Rb 00110000000 Rd := Rb/Ra, float
1
FCMP.UN Rd,Ra,Rb 010110 Rd Ra Rb 01000000000 Rd:=1if(Rb=NaNorRa=NaN,float
1
)
else
Rd := 0
FCMP.LT Rd,Ra,Rb 010110 Rd Ra Rb 01000010000 Rd := 1 if (Rb < Ra, float
1
) else
Rd := 0
FCMP.EQ Rd,Ra,Rb 010110 Rd Ra Rb 01000100000 Rd := 1 if (Rb = Ra, float
1
) else
Rd := 0
FCMP.LE Rd,Ra,Rb 010110 Rd Ra Rb 01000110000 Rd := 1 if (Rb <= Ra, float
1
) else
Rd := 0
FCMP.GT Rd,Ra,Rb 010110 Rd Ra Rb 01001000000 Rd := 1 if (Rb > Ra, float
1
) else
Rd := 0
FCMP.NE Rd,Ra,Rb 010110 Rd Ra Rb 01001010000 Rd := 1 if (Rb != Ra, float
1
) else
Rd := 0
FCMP.GE Rd,Ra,Rb 010110 Rd Ra Rb 01001100000 Rd := 1 if (Rb >= Ra, float
1
) else
Rd := 0
GET Rd,FSLx 011011 Rd 00000 0000000000000 &
FSLx
Rd := FSLx (blocking data read)
MSR[FSL] := 1 if (FSLx_S_Control = 1)
Table 1-6: MicroBlaze Instruction Set Summary (Continued)
Type A 0-5 6-10 11-15 16-20 21-31
Semantics
Type B 0-5 6-10 11-15 16-31