MicroBlaze Processor Reference Guide www.xilinx.com 21
UG081 (v6.0) June 1, 2006 1-800-255-7778
General Purpose Registers
The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The
register ﬁle is reset on bit stream download (reset value is 0x00000000).
Note: The register ﬁle is not reset by the external reset inputs: reset and debug_rst.
Please refer to Table 3-2 for software conventions on general purpose register usage.
Special Purpose Registers
Program Counter (PC)
The ProgramCounter isthe 32-bit address of the execution instruction. It can be readwith
an MFS instruction,but itcan notbe written to using an MTS instruction. Whenused with
the MFS instruction the PC register is speciﬁed by setting Sa = 0x0000.
Figure 1-2: R0-R31
Table 1-7: General Purpose Registers (R0-R31)
Bits Name Description Reset Value
0:31 R0 R0isdeﬁnedtoalwayshavethevalue
of zero. Anything written to R0 is
0:31 R1 through R13 R1 through R13 are 32-bit general
0:31 R14 32-bit used to store return addresses
0:31 R15 32-bit general purpose register -
0:31 R16 32-bit used to store return addresses
If MicroBlaze is conﬁgured to support
hardware exceptions, this register is
loaded with HW exception return
address (see also “Branch Target
Register (BTR)”); if not it is a general
0:31 R18 through R31 R18 through R31 are 32-bit general