MicroBlaze Processor Reference Guide www.xilinx.com 23
UG081 (v6.0) June 1, 2006 1-800-255-7778
Registers
R
22 EIP
Exception In Progress
0 No hardware exception in progress
1 Hardware exception in progress
Read/Write
0
23 EE
Exception Enable
0 Hardware exceptions disabled
1 Hardware exceptions enabled
Read/Write
0
24 DCE
Data Cache Enable
0 Data Cache is Disabled
1 Data Cache is Enabled
Read/Write
0
25 DZ
Division by Zero
1
0 No division by zero has occurred
1 Division by zero has occurred
Read/Write
0
26 ICE
Instruction Cache Enable
0 Instruction Cache is Disabled
1 Instruction Cache is Enabled
Read/Write
0
27 FSL
FSL Error
0 FSL get/put had no error
1 FSL get/put had mismatch in
control type
Read/Write
0
28 BIP
Break in Progress
0 No Break in Progress
1 Break in Progress
Sourceof breakcanbe softwarebreak
instruction or hardware break from
Ext_Brk or Ext_NM_Brk pin.
Read/Write
0
Table 1-9: Machine Status Register (MSR) (Continued)
Bits Name Description Reset Value