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24 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 1: MicroBlaze Architecture
R
Exception Address Register (EAR)
The Exception Address Register stores the full load/store address that caused the
exception.Foranunalignedaccessexception thatmeanstheunaligned accessaddress,and
for an DOPBexception, the failing OPBdata accessaddress. The contents ofthis registeris
undefined for all other exceptions. When read with the MFS instruction the EAR is
specified by setting Sa = 0x0003.
29 C
Arithmetic Carry
0 No Carry (Borrow)
1 Carry (No Borrow)
Read/Write
0
30 IE
Interrupt Enable
0 Interrupts disabled
1 Interrupts enabled
Read/Write
0
31 BE
Buslock Enable
2
0 Buslock disabled on data-side OPB
1 Buslock enabled on data-side OPB
Buslock Enable does not affect
operation of IXCL, DXCL, ILMB,
DLMB, or IOPB.
Read/Write
0
1. This bit is only used for integer divide-by-zero signaling. There is a floating point equivalent
in the FSR. The DZ-bit will flag divide by zero conditions regardless if the processor is
configured with exception handling or not.
2. For a details on the OPB protocol, please refer to the IBM CoreConnect specification: 64-Bit
On-Chip Peripheral Bus, Architectural Specifications, Version 2.0.
Table 1-9: Machine Status Register (MSR) (Continued)
Bits Name Description Reset Value
0 31
↑
EAR
Figure 1-5: EAR
Table 1-10: Exception Address Register (EAR)
Bits Name Description Reset Value
0:31 EAR Exception Address Register 0x00000000