MicroBlaze Processor Reference Guide www.xilinx.com 25
UG081 (v6.0) June 1, 2006 1-800-255-7778
Registers
R
Exception Status Register (ESR)
The Exception Status Register contains status bits for the processor. When read with the
MFS instruction the ESR is specified by setting Sa = 0x0005.
19 20 26 27 31
↑↑
RESERVED
DS
ESS EC
Figure 1-6: ESR
Table 1-11: Exception Status Register (ESR)
Bits Name Description Reset Value
0:18 Reserved
19 DS
Exception in delay slot.
0 not caused by delay slot instruction
1 caused by delay slot instruction
Read-only
0
20:26 ESS
Exception Specific Status
For details refer to Table 1-12.
Read-only
See Table 1-12
27:31 EC
Exception Cause
00001 = Unaligned data access exception
00010 = Illegal op-code exception
00011 = Instruction bus error exception
00100 = Data bus error exception
00101 = Divide by zero exception
00110 = Floating point unit exception
Read-only
0