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Exception Status Register (ESR)
The Exception Status Register contains status bits for the processor. When read with the
MFS instruction the ESR is speciﬁed by setting Sa = 0x0005.
19 20 26 27 31
Figure 1-6: ESR
Table 1-11: Exception Status Register (ESR)
Bits Name Description Reset Value
Exception in delay slot.
0 not caused by delay slot instruction
1 caused by delay slot instruction
Exception Speciﬁc Status
For details refer to Table 1-12.
See Table 1-12
00001 = Unaligned data access exception
00010 = Illegal op-code exception
00011 = Instruction bus error exception
00100 = Data bus error exception
00101 = Divide by zero exception
00110 = Floating point unit exception