MicroBlaze Processor Reference Guide www.xilinx.com 27
UG081 (v6.0) June 1, 2006 1-800-255-7778
Registers
R
Floating Point Status Register (FSR)
The Floating Point Status Register contains status bits for the floating point unit. It can be
readwith anMFS, andwritten withan MTS instruction. When reador written,the register
is specified by setting Sa = 0x0007.
Processor Version Register (PVR)
The Processor Version Register is controlled by the C_PVR configuration option on
MicroBlaze. When C_PVR is set to 0 the processor does not implement any PVR and
MSR[PVR]=0. If C_PVR is set to 1 then MicroBlaze implements only the first register:
PVR0, and if set to 2 all 12 PVR registers (PVR0 to PVR11) are implemented.
When read with the MFS instruction the PVR is specified by setting Sa = 0x200x, with x
being the register number between 0x0 and 0xB.
Table 1-13: Branch Target Register (BTR)
Bits Name Description Reset Value
0:31 BTR Branch target address used by handler
when returning from an exception
caused by an instruction in a delay slot
Read-only
0x00000000
27 28 29 30 31
↑↑↑↑↑
RESERVED IO DZ OF UF DO
Figure 1-8: FSR
Table 1-14: Floating Point Status Register (FSR)
Bits Name Description Reset Value
0:26 Reserved undefined
27 IO
Invalid operation
0
28 DZ
Divide-by-zero
0
29 OF
Overflow
0
30 UF
Underflow
0
31 DO
Denormalized operand error
0