28 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 1: MicroBlaze Architecture
R
Table 1-15: Processor Version Register 0 (PVR0)
Bits Name Description Value
0 CFG PVR implementation: 0=basic,
1=full
Based on C_PVR
1 BS Use barrel shifter C_USE_BARREL
2 DIV Use divider C_USE_DIV
3 MUL Use hardware multiplier C_USE_HW_MUL
4 FPU Use FPU C_USE_FPU
5 EXC Use any type of exceptions Based on C_*_EXCEPTION
6 ICU Use instruction cache C_USE_ICACHE
7 DCU Use data cache C_USE_DCACHE
8:15 Reserved 0
16:23 MBV MicroBlazereleaseversioncode
0x1 = v5.00.a
Release Specific
24:31 USR1 User configured value 1 C_PVR_USER1
Table 1-16: Processor Version Register 1 (PVR1)
Bits Name Description Value
0:31 USR2 User configured value 2 C_PVR_USER2
Table 1-17: Processor Version Register 2 (PVR2)
Bits Name Description Value
0 DOPB Data side OPB in use C_D_OPB
1 DLMB Data side LMB in use C_D_LMB
2 IOPB Instruction side OPB in use C_I_OPB
3 IOPB Instruction side OPB in use C_I_LMB
4 IRQEDGE Interrupt is edge triggered C_INTERRUPT_IS_EDGE
5 IRQPOS Interrupt edge is positive C_EDGE_IS_POSITIVE
6:16 Reserved
17 BS Use barrel shifter C_USE_BARREL
18 DIV Use divider C_USE_DIV
19 MUL Use hardware multiplier C_USE_HW_MUL
20 FPU Use FPU C_USE_FPU
21:24 Reserved