MicroBlaze Processor Reference Guide www.xilinx.com 29
UG081 (v6.0) June 1, 2006 1-800-255-7778
Registers
R
25 OP0EXEC Generate exception for 0x0
illegal opcode
C_OPCODE_0x0_ILLEGAL
26 UNEXEC Generate exception for
unaligned data access
C_UNALIGNED_EXCEPTION
27 OPEXEC Generate exception for any
illegal opcode
C_ILL_OPCODE_EXCEPTION
28 IOPBEXEC Generate exception for IOPB
error
C_IOPB_BUS_EXCEPTION
29 DOPBEXEC Generate exception for DOPB
error
C_DOPB_BUS_EXCEPTION
30 DIVEXEC Generateexception for division
by zero
C_DIV_ZERO_EXCEPTION
31 FPUEXEC Generate exceptions from FPU C_FPU_EXCEPTION
Table 1-17: Processor Version Register 2 (PVR2) (Continued)
Bits Name Description Value
Table 1-18: Processor Version Register 3 (PVR3)
Bits Name Description Value
0 DEBUG Use debug logic C_DEBUG_ENABLED
1:2 Reserved
3:6 PCBRK Number of PC breakpoints C_NUMBER_OF_PC_BRK
7:9 Reserved
10:12 RDADDR Number of read address
breakpoints
C_NUMBER_OF_RD_ADDR_B
RK
13:15 Reserved
16:18 WRADDR Number of write address
breakpoints
C_NUMBER_OF_WR_ADDR_B
RK
19:21 Reserved
22:24 FSL Number of FSLs C_FSL_LINKS
25:31 Reserved
Table 1-19: Processor Version Register 4 (PVR4)
Bits Name Description Value
0 ICU Use instruction cache C_USE_ICACHE
1:5 ICTS Instruction cache tag size C_ADDR_TAG_BITS
6 Reserved 1
7 ICW Allow instruction cache write C_ALLOW_ICACHE_WR