MicroBlaze Processor Reference Guide www.xilinx.com 31
UG081 (v6.0) June 1, 2006 1-800-255-7778
Pipeline Architecture
R
Pipeline Architecture
MicroBlaze instruction execution is pipelined. The pipeline is divided into five stages:
Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and Writeback (WB).
For most instructions, each stage takes one clock cycle to complete. Consequently, it takes
five clockcycles fora specific instruction to complete, and one instruction is completed on
every cycle. A few instructions require multiple clock cycles in the execute stage to
complete. This is achieved by stalling the pipeline.
When executing from slower memory, instruction fetches may take multiple cycles. This
additionallatency will directly affecttheefficiencyofthe pipeline. MicroBlazeimplements
an instruction prefetch buffer that reduces the impact of such multi-cycle instruction
memory latency. While the pipeline is stalled by a multi-cycle instruction in the execution
stage the prefetch buffer continues to load sequential instructions. Once the pipeline
resumes execution the fetch stage can load new instructions directly from the prefetch
buffer rather than having to wait for the instruction memory access to complete.
Table 1-25: Processor Version Register 10 (PVR10)
Bits Name Description Value
0:7 ARCH Target architecture:
0x4 = Virtex2
0x5 = Virtex2Pro
0x6 = Spartan3
0x7 = Virtex4
0x8 = Virtex5
0x9 = Spartan3E
Defined by option C_TARGET
8:31 Reserved 0
Table 1-26: Processor Version Register 11 (PVR11)
Bits Name Description Value
0:20 DO Reset value for MSR 0
21:31 RSTMSR Reset value for MSR C_RESET_MSR
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
instruction 1 IF OF EX MEM WB
instruction 2 IF OF EX MEM MEM MEM WB
instruction 3 IF OF EX Stall Stall MEM WB