32 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 1: MicroBlaze Architecture
Normally the instructions in the fetch and decode stages (as well as prefetch buffer) are
ﬂushed when executing a taken branch. The fetch pipeline stage is then reloaded with a
new instruction from the calculated branch address. A taken branch in MicroBlaze takes
threeclock cycles toexecute, twoof which are required forreﬁllingthe pipeline. To reduce
this latency overhead, MicroBlaze supports branches with delay slots.
Whenexecuting a takenbranch with delayslot, onlythe fetch pipelinestage in MicroBlaze
is ﬂushed. The instruction in the decode stage (branch delay slot) is allowed to complete.
This technique effectivelyreducesthe branchpenalty from two clockcycles to one.Branch
instructions with delay slots have a D appended to the instruction mnemonic. For
example, theBNE instructionwill notexecute the subsequent instruction (does not havea
delay slot), whereas BNED willexecute the nextinstructionbeforecontrolis transferredto
the branch location.
Adelayslotmustnot contain the followinginstructions:IMM,branch,orbreak.Interrupts
and external hardware breaks are deferred until after the delay slot branch has been
Instructions that could cause recoverable exceptions (e.g. unaligned word or halfword
load and store) are allowed in the delay slot. If an exception is caused in a delay slot the
ESR[DS] bit will be set, and the exception handler is responsible for returning the
execution to the branch target (stored in the special purpose register BTR) rather than the
sequential return address stored in R17.
MicroBlaze is implemented witha Harvard memory architecture, i.e. instruction and data
accesses are done in separate address spaces. Each address space has a 32 bit range (i.e.
handles up to 4 GByte of instructionsand data memory respectively). The instruction and
data memory ranges can be made to overlap by mapping them both to the same physical
memory. The latter is useful e.g. for software debugging.
Both instruction and data interfaces of MicroBlaze are 32 bit wide and use big endian, bit-
reversed format. MicroBlaze supports word, halfword, and byte accesses to data memory.
Data accesses must be aligned (i.e. word accesses must be on word boundaries, halfword
on halfword bounders), unless the processor is conﬁgured to support unaligned
exceptions. All instruction accesses must be word aligned.
MicroBlaze does not separate between data accesses to I/O and memory (i.e. it uses
Memory Bus (LMB), On-Chip Peripheral Bus (OPB), and Xilinx CacheLink (XCL). The
LMB memory address range must not overlap with OPB or XCL ranges.
MicroBlaze has a single cycle latency for accesses to local memory (LMB) and for cache
read hits. A data cache write normally has two cycles of latency (more if the posted-write
buffer in the memory controller is full).
For details on the different memory interfaces please refer to Chapter 2, “MicroBlaze
Signal Interface Description”.