MicroBlaze Processor Reference Guide www.xilinx.com 33
UG081 (v6.0) June 1, 2006 1-800-255-7778
Reset, Interrupts, Exceptions, and Break
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Reset, Interrupts, Exceptions, and Break
MicroBlazesupports reset, interrupt, userexception, break, and hardwareexceptions. The
following section describes the execution flow associated with each of these events.
The relative priority starting with the highest is:
1. Reset
2. Hardware Exception
3. Non-maskable Break
4. Break
5. Interrupt
6. User Vector (Exception)
Table 1-27 defines the memory address locations of the associated vectors and the
hardware enforced register file locations for return address. Each vector allocates two
addresses to allow full address range branching (requires an IMM followed by a BRAI
instruction). The address range 0x28 to 0x4F is reserved for future software support by
Xilinx. Allocating these addresses for user applications is likely to conflict with future
releases of EDK support software.
Table 1-27: Vectors and Return Address Register File Location
Event Vector Address
Register File
Return Address
Reset 0x00000000 -
0x00000004
-
User Vector (Exception) 0x00000008 -
0x0000000C
-
Interrupt 0x00000010 -
0x00000014
R14
Break: Non-maskable
hardware
0x00000018 -
0x0000001C
R16
Break: Hardware
Break: Software
Hardware Exception 0x00000020 -
0x00000024
R17 or BTR
Reserved by Xilinx for
future use
0x00000028 -
0x0000004F
-