36 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 1: MicroBlaze Architecture
Software Breaks
To perform a software break, use the brk and brki instructions. Refer to Chapter 4,
“MicroBlaze Instruction Set Architecture” for detailed information on software breaks.
The time it will take MicroBlaze to enter a break service routine from the time the break
occurs, depends on the instruction currently in the execution stage and the latency to the
memory storing the break vector.
Equivalent Pseudocode
r16 PC
MicroBlaze supports one external interrupt source (connecting to the Interrupt input
port). The processor will only react to interrupts if the Interrupt Enable (IE) bit in the
Machine Status Register (MSR) is set to 1. On an interrupt the instruction in the execution
stagewill complete, whilethe instruction inthe decode stageis replaced by abranch to the
interrupt vector (address 0x10). The interrupt return address (the PC associated with the
instruction in the decode stage at the time of the interrupt) is automatically loaded into
general purpose register R14. In addition, the processor also disables future interrupts by
clearing the IE bit in the MSR. The IE bit is automatically set again when executing the
RTID instruction.
Interrupts are ignored by theprocessor if either of thebreak in progress (BIP) or exception
in progress (EIP) bits in the MSR are set to 1.
The time it will take MicroBlaze to enter an Interrupt Service Routine (ISR) from the time
an interrupt occurs depends on the configuration of the processor and the latency of the
memory controller storing the interrupt vectors. If MicroBlaze is configured to have a
hardware divider, the largest latency will happen when an interrupt occurs during the
execution of a division instruction.
Equivalent Pseudocode
r14 PC
User Vector (Exception)
Theuser exception vectoris locatedat address0x8. A userexception is causedby inserting
a ‘BRALID Rx,0x8’ instruction in the software flow. Although Rx could be any general
purpose register Xilinx recommends using R15 for storing the user exception return
address, and to use the RTSD instruction to return from the user exception handler.
rx PC