MicroBlaze Processor Reference Guide www.xilinx.com 37
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instruction Cache
R
PC 0x00000008
Instruction Cache
Overview
MicroBlaze may be used with an optional instruction cache for improved performance
when executing code that resides outside the LMB address range.
The instruction cache has the following features:
Direct mapped (1-way associative)
User selectable cacheable memory address range
Configurable cache and tag size
Caching over CacheLink (XCL) interface
Option to use 4 or 8 word cache-line
Cache on and off controlled using a bit in the MSR
Optional WIC instruction to invalidate instruction cache lines
General Instruction Cache Functionality
When the instruction cache is used, the memory address space in split into two segments:
a cacheable segment and a non-cacheable segment. The cacheable segment is determined
by two parameters: C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR. All
addresses within this range correspond to the cacheable address segment. All other
addresses are non-cacheable.
The cacheable instruction address consists of two parts: the cache address, and the tag
address. The MicroBlaze instruction cache can be configured from 2kB to 64 kB. This
correspondstoacache addressofbetween11and16bits.The tagaddresstogetherwiththe
cache address should match the full address of cacheable memory.
Figure 1-9: Instruction Cache Organization
Instruction Address Bits
0 3031
Cache Address
Tag Address
-
-
Tag
Instruction
BRAM
BRAM
Line Addr
Word Addr
=
Tag
Valid (word and line)
Cache_Hit
Cache_instruction_data