40 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 1: MicroBlaze Architecture
R
Aloadfromanaddresswithinthecacheable range will,providedthatthecacheisenabled,
trigger a checkto determineif the requesteddata is currentlycached. Ifit is(i.e. on acache-
hit) the requested data is retrieved from the cache. If not (i.e. on a cache-miss) the address
is requested over data CacheLink (DXCL), and the processor pipeline will stall until the
cache line associated to the requested address is returned from the external memory
controller.
Data Cache Software Support
MSR Bit
The DCE bit in the MSR controls whether or not the cache is enabled. When disabling
caches the user must ensure that all the prior writes within the cacheable range has been
completed in externalmemory before reading back over OPB.This can bedone by writing
to a semaphore immediately before turning off caches, and then in a loop poll the
semaphore until it has been written.
The contents of the cache is preserved when the cache is disabled.
WDC Instruction
The optional WDC instruction (C_ALLOW_DCACHE_WR=1) is used to invalidate cache
lines in the data cache from an application. For a detailed description, please refer to
Chapter 4, “MicroBlaze Instruction Set Architecture”.
Floating Point Unit (FPU)
Overview
The MicroBlaze floating point unit is based on the IEEE 754 standard:
Uses IEEE754 single precision floatingpoint format, including definitionsfor infinity,
not-a-number (NaN), and zero
Supports addition, subtraction, multiplication, division, and comparison instructions
Implements round-to-nearest mode
Generates sticky status bits for: underflow, overflow, and invalid operation
For improved performance, the following non-standard simplifications are made:
Denormalized
(1)
operands are not supported.A hardwarefloating point operation on
a denormalized number will return a quiet NaN and set the denormalized operand
error bit in FSR; see "Floating Point Status Register (FSR)" on page 27
A denormalized result is stored as a signed 0 with the underflow bit set in FSR. This
method is commonly referred to as Flush-to-Zero (FTZ)
An operation on a quiet NaN will return the fixed NaN: 0xFFC00000, rather than one
of the NaN operands
Overflow as a result of a floating point operation will always return signed ∞, even
when the exception is trapped.
1. Numbers that are so close to 0, that theycannot be represented withfull precision, i.e. any number n that falls
in the following ranges: ( 1.17549*10
-38
> n > 0 ), or ( 0 > n > -1.17549 * 10
-38
)