MicroBlaze Processor Reference Guide www.xilinx.com 41

UG081 (v6.0) June 1, 2006 1-800-255-7778

Floating Point Unit (FPU)

R

Format

An IEEE 754 single precision ﬂoating point number is composed of the following three

ﬁelds:

1. 1-bit sign

2. 8-bit biased exponent

3. 23-bit fraction (a.k.a. mantissa or signiﬁcand)

The ﬁelds are stored in a 32 bit word as deﬁned in Figure 1-11:

The value of a ﬂoating point number v in MicroBlaze has the following interpretation:

1. If exponent = 255 and fraction <> 0, then v= NaN, regardless of the sign bit

2. If exponent = 255 and fraction = 0, then v= (-1)

sign

* ∞

3. If 0 < exponent < 255, then v = (-1)

sign

* 2

(exponent-127)

* (1.fraction)

4. If exponent = 0 and fraction <> 0, then v = (-1)

sign

* 2

-126

* (0.fraction)

5. If exponent = 0 and fraction = 0, then v = (-1)

sign

* 0

Forpracticalpurposes only3and5arereallyuseful, whiletheothersallrepresenteitheran

error or numbers that can no longer be represented with full precision in a 32 bit format.

Rounding

The MicroBlaze FPU only implements the default rounding mode, “Round-to-nearest”,

speciﬁedinIEEE 754. Bydeﬁnition,theresultofanyﬂoatingpointoperationshouldreturn

the nearest single precision value to the inﬁnitely precise result. If the two nearest

representable values are equally near, then the one with its least signiﬁcant bit zero is

returned.

Operations

All MicroBlaze FPU operations use the processors general purpose registers rather than a

dedicated ﬂoating point register ﬁle, see “General Purpose Registers”.

Arithmetic

The FPU implements the following ﬂoating point operations:

• addition, fadd

• subtraction, fsub

• multiplication, fmul

• division, fdiv

01 9 31

↑↑ ↑

sign exponent fraction

Figure 1-11: IEEE 754 Single Precision format