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46 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 2: MicroBlaze Signal Interface Description
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Figure 2-1: MicroBlaze Core Block Diagram
DXCL_M
DXCL_S
Data-sideInstruction-side
DOPB
DLMB
IOPB
ILMB
bus interface bus interface
Instruction
Buffer
Program
Counter
Register File
32 X 32b
ALU
Instruction
Decode
Bus
IF
Bus
IF
MFSL 0..7
SFSL 0..7
IXCL_M
IXCL_S
I-Cache
D-Cache
Shift
Barrel Shift
Multiplier
Divider
FPU
Special
Purpose
Registers
Optional MicroBlaze feature
Table 2-1: Summary of MicroBlaze Core I/O
Signal Interface I/O Description
DM_ABus[0:31] DOPB O Data interface OPB address bus
DM_BE[0:3] DOPB O Data interface OPB byte enables
DM_busLock DOPB O Data interface OPB bus lock
DM_DBus[0:31] DOPB O Data interface OPB write data bus
DM_request DOPB O Data interface OPB bus request
DM_RNW DOPB O Data interface OPB read, not write
DM_select DOPB O Data interface OPB select
DM_seqAddr DOPB O Data interface OPB sequential address
DOPB_DBus[0:31] DOPB I Data interface OPB read data bus
DOPB_errAck DOPB I Data interface OPB error acknowledge
DOPB_MGrant DOPB I Data interface OPB bus grant
DOPB_retry DOPB I Data interface OPB bus cycle retry
DOPB_timeout DOPB I Data interface OPB timeout error
DOPB_xferAck DOPB I Data interface OPB transfer
acknowledge
IM_ABus[0:31] IOPB O Instruction interface OPB address bus