MicroBlaze Processor Reference Guide www.xilinx.com 47
UG081 (v6.0) June 1, 2006 1-800-255-7778
MicroBlaze I/O Overview
R
IM_BE[0:3] IOPB O Instruction interface OPB byte enables
IM_busLock IOPB O Instruction interface OPB bus lock
IM_DBus[0:31] IOPB O InstructioninterfaceOPBwrite databus
(always 0x00000000)
IM_request IOPB O Instruction interface OPB bus request
IM_RNW IOPB O InstructioninterfaceOPBread,notwrite
(tied to IM_select)
IM_select IOPB O Instruction interface OPB select
IM_seqAddr IOPB O Instruction interface OPB sequential
address
IOPB_DBus[0:31] IOPB I Instruction interface OPB read data bus
IOPB_errAck IOPB I Instruction interface OPB error
acknowledge
IOPB_MGrant IOPB I Instruction interface OPB bus grant
IOPB_retry IOPB I Instruction interfaceOPB buscycle retry
IOPB_timeout IOPB I Instruction interface OPB timeout error
IOPB_xferAck IOPB I Instruction interface OPB transfer
acknowledge
Data_Addr[0:31] DLMB O Data interface LMB address bus
Byte_Enable[0:3] DLMB O Data interface LMB byte enables
Data_Write[0:31] DLMB O Data interface LMB write data bus
D_AS DLMB O Data interface LMB address strobe
Read_Strobe DLMB O Data interface LMB read strobe
Write_Strobe DLMB O Data interface LMB write strobe
Data_Read[0:31] DLMB I Data interface LMB read data bus
DReady DLMB I Data interface LMB data ready
Instr_Addr[0:31] ILMB O Instruction interface LMB address bus
I_AS ILMB O Instruction interface LMB address
strobe
IFetch ILMB O Instruction interface LMB instruction
fetch
Instr[0:31] ILMB I Instruction interface LMB read data bus
IReady ILMB I Instruction interface LMB data ready
FSL0_M .. FSL7_M MFSL O Master interface to output FSL channels
FSL0_S .. FSL7_S SFSL I Slave interface to input FSL channels
ICache_FSL_in... IXCL_S IO Instruction side CacheLink FSL slave
interface
Table 2-1: Summary of MicroBlaze Core I/O (Continued)
Signal Interface I/O Description