MicroBlaze Processor Reference Guide www.xilinx.com 53
UG081 (v6.0) June 1, 2006 1-800-255-7778
Local Memory Bus (LMB) Interface Description
Read and Write Data Steering
The MicroBlaze data-side bus interface performs the read steering and write steering
required to support the following transfers:
byte, halfword, and word transfers to word devices
byte and halfword transfers to halfword devices
byte transfers to byte devices
MicroBlaze does not support transfers that are larger than the addressed device. These
typesof transfers requiredynamic bussizing andconversion cycles thatarenot supported
by the MicroBlaze bus interface. Data steering for read cycles is shown in Table 2-4, and
data steering for write cycles is shown in Table 2-5
Note that other OPB masters may have more restrictive requirements for byte lane
placement than those allowed by MicroBlaze. OPB slave devices are typically attached
“left-justified” with byte devices attached to the most-significant byte lane, and halfword
devices attachedto themost significanthalfword lane. The MicroBlaze steering logic fully
supports this attachment method.
Table 2-4: Read Data Steering (load to Register rD)
Register rD Data
rD[0:7] rD[8:15] rD[16:23] rD[24:31]
11 0001 byte Byte3
10 0010 byte Byte2
01 0100 byte Byte1
00 1000 byte Byte0
10 0011 halfword Byte2 Byte3
00 1100 halfword Byte0 Byte1
00 1111 word Byte0 Byte1 Byte2 Byte3
Table 2-5: Write Data Steering (store from Register rD)
Write Data Bus Bytes
Size Byte0 Byte1 Byte2 Byte3
11 0001 byte rD[24:31]
10 0010 byte rD[24:31]
01 0100 byte rD[24:31]
00 1000 byte rD[24:31]
10 0011 halfword rD[16:23] rD[24:31]
00 1100 halfword rD[16:23] rD[24:31]
00 1111 word rD[0:7] rD[8:15] rD[16:23] rD[24:31]