56 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 2: MicroBlaze Signal Interface Description
The MicroBlaze CacheLink interface can also connect to an Fast Simplex Link (FSL)
interfaced memory controller via explicitly instantiated FSL master/slave pair, however
this topology is considered deprecated and is not recommended for new designs.
The interface is only available on MicroBlaze when caches are enabled. It is legal to use a
CacheLink cache on the instruction side or the data side without caching the other.
Memory locations outside the cacheable range are accessed over OPB or LMB. Cached
memory range is accessed over OPB whenever the caches are software disabled (i.e.
MSR[DCE]=0 or MSR[ICE]=0).
The CacheLink cache controllershandle 4or 8-wordcache lineswith criticalwordfirst. At
the same time the separation from the OPB bus reduces contention for non-cached
memory accesses.
CacheLink Signal Interface
The CacheLink signals on MicroBlaze are listed in Table 2-8
Table 2-8: MicroBlaze Cache Link signals
Signal Name Description VHDL Type Direction
ICACHE_FSL_IN_Clk Clock output to I-side
return read data FSL
std_logic output
ICACHE_FSL_IN_Read Read signal to I-side
return read data FSL.
std_logic output
ICACHE_FSL_IN_Data Read data from I-side
return read data FSL
(0 to 31)
ICACHE_FSL_IN_Control FSL control-bit from I-
Reserved for future use
std_logic input
ICACHE_FSL_IN_Exists More read data exists in I-
side return FSL
std_logic input
ICACHE_FSL_OUT_Clk Clock output to I-side
read access FSL
std_logic output
ICACHE_FSL_OUT_Write Write new cache miss
access request to I-side
read access FSL
std_logic output
ICACHE_FSL_OUT_Data Cache miss access
(=address) to I-side read
access FSL
(0 to 31)
ICACHE_FSL_OUT_Control FSL control-bit to I-side
for future use
std_logic output
ICACHE_FSL_OUT_Full FSL access buffer for I-
side read accesses is full
std_logic input
DCACHE_FSL_IN_Clk Clock output to D-side
return read data FSL
std_logic output