MicroBlaze Processor Reference Guide www.xilinx.com 61
UG081 (v6.0) June 1, 2006 1-800-255-7778
MicroBlaze Core Congurability
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MicroBlaze Core Congurability
The MicroBlaze core has been developed to support a high degree of user configurability.
This allows tailoring of the processor to meet specific cost/performance requirements.
Configurationisdonevia parameters that typically: enable, size,orselectcertainprocessor
features. E.g. the instruction cache is enabled by setting the C_USE_ICACHE parameter.
The size of the instruction cache, and the cacheable memory range, are all configurable
using: C_CACHE_BYTE_SIZE, C_ICACHE_BASEADDR, and C_ICACHE_HIGHADDR
respectively.
Trace_OF_PipeRun Pipeline advance for
Decode stage
std_logic output
Trace_EX_PipeRun Pipeline advance for
Execution stage
std_logic output
Trace_MEM_PipeRun Pipeline advance for
Memory stage
std_logic output
1. Valid only when Trace_Valid_Instr = 1
Table 2-11: Type of Trace Exception
Trace_Exception_Kind [0:3] Description
0001 Unaligned execption
0010 Illegal Opcode exception
0011 Instruction Bus exception
0100 Data Bus exception
0101 Div by Zero exception
0110 FPU exception
1001 Debug exception
1010 Interrupt
1011 External non maskable break
1100 External maskable break
Table 2-10: MicroBlaze Trace signals
Signal Name Description VHDL Type Direction