64 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 2: MicroBlaze Signal Interface Description
R
C_ICACHE_HIGHADDR Instruction cache high
address
0x00000000-
0xFFFFFFFF
0x3FFF
FFFF
std_logi
c_vector
C_USE_ICACHE Instruction cache 0, 1 0 integer
C_ALLOW_ICACHE_WR Instruction cache write
enable
0, 1 1 integer
C_ICACHE_LINELEN Instruction cache line
length
4, 8 4 integer
C_ADDR_TAG_BITS Instruction cache address
tags
0-21 17 yes integer
C_CACHE_BYTE_SIZE Instruction cache size 2048, 4096,
8192, 16384,
32768,
65536
1
8192 integer
C_ICACHE_USE_FSL Cache over CacheLink
instead of OPB for
instructions
1 1 integer
C_DCACHE_BASEADDR Data cache base address 0x00000000-
0xFFFFFFFF
0x0000
0000
std_logi
c_vector
C_DCACHE_HIGHADDR Data cache high address 0x00000000-
0xFFFFFFFF
0x3FFF
FFFF
std_logi
c_vector
C_USE_DCACHE Data cache 0,1 0 integer
C_ALLOW_DCACHE_WR Data cache write enable 0,1 1 integer
C_DCACHE_LINELEN Data cache line length 4, 8 4 integer
C_DCACHE_ADDR_TAG Data cache address tags 0-20 17 yes integer
C_DCACHE_BYTE_SIZE Data cache size 2048, 4096,
8192, 16384,
32768,
65536
2
8192 integer
C_DCACHE_USE_FSL Cache over CacheLink
instead of OPB for data
1 1 integer
1. Not all sizes are permitted in all architectures. The cache will use between 1 and 32 RAMB primitives.
2. Not all sizes are permitted in all architectures. The cache will use between 1 and 32 RAMB primitives.
Table 2-12: MPD Parameters
Parameter Name Feature/Description
Allowable
Values
Default
Value
EDK Tool
Assigned
VHDL
Type