70 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 3: MicroBlaze Application Binary Interface
R
Interrupt and Exception Handling
MicroBlaze assumes certain address locations for handling interrupts and exceptions as
indicated in Table 3-3. At these locations, code is written to jump to the appropriate
handlers.
The code expected at these locations is as shown in Figure 3-3. For programs compiled
without the -xl-mode-xmdstub compiler option, the crt0.o initialization file is passed by
themb-gcccompiler tothemb-ld linkerforlinking.Thisfile sets theappropriateaddresses
of the exception handlers.
For programs compiled with the -xl-mode-xmdstub compiler option, the crt1.o
initialization file is linked to the output program. This program has to be run with the
xmdstub already loaded in the memory at address location 0x0. Hence at run-time, the
initializationcode in crt1.owritestheappropriateinstructionstolocation 0x8through0x14
depending on the address of the exception and interrupt handlers.
Figure 3-3: Code for passing control to exception and interrupt handlers
MicroBlaze allows exception and interrupt handler routines to be located at any address
location addressable using 32 bits. The user exception handler code starts with the label
_exception_handler, thehardwareexception handler startswith _hw_exception_handler,
while the interrupt handler code starts with the label _interrupt_handler.
In the current MicroBlaze system, there are dummy routines for interrupt and exception
handling, which you can change. In order to override these routines and link your
interrupt and exception handlers, you must define the interrupt handler code with an
attribute interrupt_handler. For more details about the use and syntax of the interrupt
handler attribute, please refer to the GNU Compiler Tools chapter in the document: UG111
Embedded System Tools Reference Manual.
Table 3-3: Interrupt and Exception Handling
On Hardware jumps to Software Labels
Start / Reset 0x0 _start
User exception 0x8 _exception_handler
Interrupt 0x10 _interrupt_handler
Break (HW/SW) 0x18 -
Hardware exception 0x20 _hw_exception_handler
Reserved by Xilinx for
future use
0x28 - 0x4F
-
0x00: bri _start1
0x04: nop
0x08: imm high bits of address (user exception handler)
0x0c: bri _exception_handler
0x10: imm high bits of address (interrupt handler)
0x14: bri _interrupt_handler
0x20: imm high bits of address (HW exception handler)
0x24: bri _hw_exception_handler