MicroBlaze Processor Reference Guide www.xilinx.com 73
UG081 (v6.0) June 1, 2006 1-800-255-7778
The sum of the contents of registers rA and rB, is placed into register rD.
Bit3 of theinstruction (labeledas K inthe ﬁgure)is set toa onefor themnemonic addk.Bit
4 of the instruction (labeled as C in the ﬁgure) is set to a one for the mnemonic addc. Both
bits are set to a one for the mnemonic addkc.
When an add instruction has bit 3 set (addk, addkc), the carry ﬂag will Keep its previous
value regardless of the outcome of the execution of the instruction. If bit 3 is cleared (add,
addc), then the carry ﬂag will be affected by the execution of the instruction.
When bit 4 of the instruction is set to a one (addc, addkc), the content of the carry ﬂag
(MSR[C]) affects the execution of the instruction. When bit 4 is cleared (add, addk), the
contentofthecarryﬂag doesnotaffecttheexecution oftheinstruction(providinganormal
if C = 0 then
(rD) ← (rA) + (rB)
(rD) ← (rA) + (rB) + MSR[C]
if K = 0 then
MSR[C] ← CarryOut
The C bit in the instruction opcode is not the same as the carry bit in the MSR.
The “add r0, r0, r0” (= 0x00000000) instruction is never used by the compiler and usually
indicatesuninitialized memory. If youareusing illegal instruction exceptions youcan trap
these instructions by setting the MicroBlaze option C_OPCODE_0x0_ILLEGAL=1
rD, rA, rB Add
rD, rA, rB Add with Carry
rD, rA, rB Add and Keep Carry
rD, rA, rB Add with Carry and Keep Carry
0 0 0 K C 0 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31