MicroBlaze Processor Reference Guide www.xilinx.com 77
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
andn
Logical AND NOT
Description
The contents of register rA are ANDed with the logical complement of the contents of
register rB; the result is placed into register rD.
Pseudocode
(rD) (rA) (rB)
Registers Altered
rD
Latency
1 cycle
andn rD, rA, rB
1 0 0 0 1 1 rD rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31