78 www.xilinx.com MicroBlaze Processor Reference Guide
1-800-255-7778 UG081 (v6.0) June 1, 2006
Chapter 4: MicroBlaze Instruction Set Architecture
R
andni
Logical AND NOT with Immediate
Description
The IMM field is sign-extended to 32 bits. The contentsof register rA are ANDed with the
logical complement of the extended IMM field; the result is placed into register rD.
Pseudocode
(rD) (rA) (sext(IMM))
Registers Altered
rD
Latency
1 cycle
Note
By default, Type BInstructionswill take the16-bit IMM fieldvalue and sign extendit to 32
bits to use as the immediate operand. This behavior can be overridden by preceding the
Type B instruction with an imm instruction. See the imm instruction for details on using
32-bit immediate values.
andni rD, rA, IMM
1 0 1 0 1 1 rD rA IMM
0 6 11 16 31