MicroBlaze Processor Reference Guide www.xilinx.com 85
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
ble
Branch if Less or Equal
Description
Branch if rA is less or equal to 0, to the instruction located in the offset value of rB. The
target of the branch will be the instruction at address PC + rB.
Themnemonicbledwillsetthe D bit. The Dbitdetermineswhetherthereisabranchdelay
slotor not. Ifthe D bitis set, itmeans that thereisa delay slotand theinstructionfollowing
the branch(i.e. inthe branchdelay slot) is allowed to complete executionbeforeexecuting
the target instruction. If the D bit is not set, it means that there is no delay slot, so the
instruction to be executed after the branch is the target instruction.
Pseudocode
If rA <= 0 then
PC
PC + rB
else
PC
PC + 4
if D = 1 then
allow following instruction to complete execution
Registers Altered
PC
Latency
1 cycle (if branch is not taken)
2 cycles (if branch is taken and the D bit is set)
3 cycles (if branch is taken and the D bit is not set)
Note
A delay slot must not be used by the following: IMM, branch, or break instructions. This
also applies to instructions causing recoverable exceptions (e.g. unalignement), when
hardware exceptions are enabled. Interrupts and external hardware breaks are deferred
until after the delay slot branch has been completed.
ble rA, rB Branch if Less or Equal
bled rA, rB Branch if Less or Equal with Delay
1 0 0 1 1 1 D 0 0 1 1 rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31