MicroBlaze Processor Reference Guide www.xilinx.com 87
UG081 (v6.0) June 1, 2006 1-800-255-7778
Instructions
R
blt
Branch if Less Than
Description
Branch if rA is less than 0, to the instruction located in the offset value of rB. The target of
the branch will be the instruction at address PC + rB.
Themnemonic bltd willset theD bit.The Dbit determineswhether there is abranch delay
slotor not. Ifthe D bitis set, itmeans that thereisa delay slotand theinstructionfollowing
the branch(i.e. inthe branchdelay slot) is allowed to complete executionbeforeexecuting
the target instruction. If the D bit is not set, it means that there is no delay slot, so the
instruction to be executed after the branch is the target instruction.
Pseudocode
If rA < 0 then
PC
PC + rB
else
PC
PC + 4
if D = 1 then
allow following instruction to complete execution
Registers Altered
PC
Latency
1 cycle (if branch is not taken)
2 cycles (if branch is taken and the D bit is set)
3 cycles (if branch is taken and the D bit is not set)
Note
A delay slot must not be used by the following: IMM, branch, or break instructions. This
also applies to instructions causing recoverable exceptions (e.g. unalignement), when
hardware exceptions are enabled. Interrupts and external hardware breaks are deferred
until after the delay slot branch has been completed.
blt rA, rB Branch if Less Than
bltd rA, rB Branch if Less Than with Delay
1 0 0 1 1 1 D 0 0 1 0 rA rB 0 0 0 0 0 0 0 0 0 0 0
0 6 11 16 21 31